iCE40/ghdl - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	synth: special handling of 'const' functions.	Tristan Gingold	2019-09-30	1	-0/+3
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*	synth: refactoring of alias (allow alias of anything).	Tristan Gingold	2019-09-30	1	-2/+2
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*	synth: introduce type_logic	Tristan Gingold	2019-09-29	1	-1/+5
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*	synth: introduce type_unbounded_vector.	Tristan Gingold	2019-09-22	1	-0/+4
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*	synth: remove value_mux2.	Tristan Gingold	2019-09-18	1	-10/+0
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*	synth: fold addition on constant nets.	Tristan Gingold	2019-09-17	1	-1/+3
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*	synth: extract synth-oper from synth-expr	Tristan Gingold	2019-09-12	1	-0/+3
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*	synth: improve support of return statement.	Tristan Gingold	2019-09-11	1	-0/+2
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*	synth: introduce slice type.	Tristan Gingold	2019-09-11	1	-0/+7
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*	synth: Add width field in type_type record.	Tristan Gingold	2019-09-11	1	-3/+6
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*	synth: handle alias (WIP, read only).	Tristan Gingold	2019-09-11	1	-1/+10
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*	synth: handle const record aggregates.	Tristan Gingold	2019-09-05	1	-4/+9
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*	synth: add value_const_array.	Tristan Gingold	2019-09-05	1	-1/+9
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*	synth: add support for record types.	Tristan Gingold	2019-08-29	1	-5/+16
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*	synth: add support for memories.	Tristan Gingold	2019-07-29	1	-2/+10
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*	synth: remove extract_bound (trivial).	Tristan Gingold	2019-07-28	1	-2/+0
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*	synth: unconstrained arrays.	Tristan Gingold	2019-07-28	1	-0/+7
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*	synth: preliminary support of dynamic indexing.	Tristan Gingold	2019-07-28	1	-84/+111
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*	synth: rework range.	Tristan Gingold	2019-07-26	1	-0/+6
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*	synth: preliminary support of integer subtypes.	Tristan Gingold	2019-07-26	1	-0/+2
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*	synth: fix aggregate vectorize direction.	Tristan Gingold	2019-07-20	1	-0/+1
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*	synth: handle instantiation (WIP)	Tristan Gingold	2019-07-10	1	-0/+2
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*	synth: handle slice assignment.	Tristan Gingold	2019-06-25	1	-0/+1
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*	synth: remove unused Value_Logic.	Tristan Gingold	2019-06-23	1	-7/+0
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*	synth: handle more predefined functions.	Tristan Gingold	2019-06-23	1	-1/+6
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*	synth: get rid of execution and elaboration.	Tristan Gingold	2019-06-19	1	-25/+104
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*	synth: support conditional signal assignments.	Tristan Gingold	2019-06-08	1	-0/+10
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*	synth: add comments and refactoring.	Tristan Gingold	2019-06-07	1	-19/+18
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*	vhdl: rename iirs to vhdl.nodes	Tristan Gingold	2019-05-05	1	-1/+1
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*	Create the simul.ads package (for a namespace).	Tristan Gingold	2017-11-24	1	-2/+2
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*	simulation: refactoring (move block_instance to iir_values).	Tristan Gingold	2017-11-24	1	-2/+0
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*	Add netlist generation infrastructure.	Tristan Gingold	2017-01-31	1	-0/+120