iCE40/ghdl - clone of https://github.com/ghdl/ghdl

	Commit message (Collapse)	Author	Age	Files	Lines
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*	synth-oper: refactoring for std_match.	Tristan Gingold	2020-03-09	1	-81/+91
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*	synth: handle user-defined operator call.	Tristan Gingold	2020-03-08	3	-107/+202
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*	synth-static_oper: handle const operands for enums.	Tristan Gingold	2020-03-07	1	-3/+6
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*	synth-stmts: handle constant if statements.	Tristan Gingold	2020-03-07	1	-0/+1
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*	netlists-builders: handle null operands for dyadic operations.	Tristan Gingold	2020-03-07	1	-1/+0
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*	netlists-expands: fix dyn_insert_en (en was missing). Fix #1155	Tristan Gingold	2020-03-07	2	-1/+4
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*	synthesis: handle initialized output ports.	Tristan Gingold	2020-03-07	7	-25/+72
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*	netlists-disp_vhdl: handle xnor. Fix #1153	Tristan Gingold	2020-03-07	1	-0/+2
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*	Remove redundant pragma inline.	Tristan Gingold	2020-03-06	1	-1/+0
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*	synth: fix conversion of net to constant for physical values. Fix #1148	Tristan Gingold	2020-03-02	2	-6/+11
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*	synth: top entity name is not anymore hashed by default.	Tristan Gingold	2020-03-01	5	-81/+125
\| \| \| \|	Use --top-name=hash to get the previous behaviour.
*	synth-insts: add comments, minor refactoring.	Tristan Gingold	2020-02-29	3	-9/+6
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*	synth: handle more physical operators. Fix #1146	Tristan Gingold	2020-02-29	4	-21/+80
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*	synth-static_oper: handle enum inequality.	Tristan Gingold	2020-02-29	1	-0/+3
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*	synth-decls: fix handling of record subtypes.	Tristan Gingold	2020-02-29	1	-1/+14
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*	synth: handle file_close.	Tristan Gingold	2020-02-27	3	-10/+31
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*	synth-static_oper: handle to_stdlogicvector_bv	Tristan Gingold	2020-02-27	1	-1/+20
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*	netlists: rework memories to fix port orders, add a loop.	Tristan Gingold	2020-02-23	7	-46/+85
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*	netlists-memories: also reduce muxes for extract.	Tristan Gingold	2020-02-21	1	-7/+35
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*	synth-decls: handle alias declaration without subtype indication.	Tristan Gingold	2020-02-21	1	-2/+7
\| \| \| \|	Fix #1144
*	netlists-memories: factorize code.	Tristan Gingold	2020-02-20	1	-235/+191
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*	netlists-inference: preliminary work to support else in synch code.	Tristan Gingold	2020-02-20	1	-71/+153
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*	netlists: add midff	Tristan Gingold	2020-02-20	3	-0/+47
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*	vhdl: recognize conversion functions from std_logic_1164	Tristan Gingold	2020-02-18	1	-1/+2
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*	synth: rework static predefined function calls.	Tristan Gingold	2020-02-18	3	-152/+224
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*	synth: handle file_open.	Tristan Gingold	2020-02-18	3	-0/+48
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*	synth-environment: handle unassigned outputs.	Tristan Gingold	2020-02-18	1	-6/+8
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*	netlists-cleanup: refactoring.	Tristan Gingold	2020-02-18	1	-12/+17
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*	synth-insts: handle slices in individual associations.	Tristan Gingold	2020-02-18	1	-0/+21
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*	synth-expr: handle anonymous signal declarations.	Tristan Gingold	2020-02-18	2	-6/+10
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*	synth: allow constant condition for if-generate statement.	Tristan Gingold	2020-02-17	1	-0/+1
\| \| \| \|	For #1076
*	synth: add mdff.	Tristan Gingold	2020-02-17	4	-12/+88
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*	netlists-inference: remove useless code.	Tristan Gingold	2020-02-16	1	-10/+0
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*	synthesis: rework memory inference.	Tristan Gingold	2020-02-16	3	-32/+101
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*	synth: handle component with ports in different order.	Tristan Gingold	2020-02-13	3	-45/+46
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*	synth-static_oper: handle more division operands. Fix #1134	Tristan Gingold	2020-02-12	1	-1/+2
\| \| \| \|	From donnie-j
*	synth: handle null vector for vec-vec concat. Fix #1133	Tristan Gingold	2020-02-11	2	-6/+12
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*	synth-oper: handle add for (natural, unsigned). Fix #1132	Tristan Gingold	2020-02-11	1	-0/+15
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*	netlists-memories: handle split memories. Fix #1127	Tristan Gingold	2020-02-11	1	-8/+18
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*	synth-static_oper: handle xor.	Tristan Gingold	2020-02-10	1	-0/+11
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*	synth-expr: implement value and val attributes. Fix #1130	Tristan Gingold	2020-02-10	1	-1/+39
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*	synth: remove remaining clock edge gates after memories.	Tristan Gingold	2020-02-10	2	-0/+26
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*	netlists-memories: cleanup.	Tristan Gingold	2020-02-10	1	-319/+1
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*	synth: rework (again) memory inference.	Tristan Gingold	2020-02-10	8	-80/+312
\| \| \| \| \| \|	Preliminary work to support multi-clock memories. Strengthen and fix fallout of Check_Connected. Rename synth.inference to netlists.inference.
*	synth-inference: minor refactoring.	Tristan Gingold	2020-02-06	1	-24/+7
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*	synth-decls: set a default value to non-assigned signals. Fix #1107	Tristan Gingold	2020-02-05	1	-1/+3
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*	netlists-disp_vhdl: handle 1-bit const_x. For #1107	Tristan Gingold	2020-02-05	1	-3/+9
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*	synth-inference: use the mux output to detect end of walk. Fix #1122	Tristan Gingold	2020-02-01	1	-1/+8
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*	synth-oper: handle std_match for slv. Close #1121	Tristan Gingold	2020-01-31	1	-1/+2
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*	netlists-expands: also handle ror.	Tristan Gingold	2020-01-30	1	-7/+24
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