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path: root/src/vhdl/translate/trans_analyzes.adb
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* vhdl: renames disp_vhdl to printsTristan Gingold2019-05-301-2/+2
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* Add simple_IO - to be used instead of Text_IO.Tristan Gingold2019-05-191-3/+3
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* vhdl: extract vhdl.errors from errorout.Tristan Gingold2019-05-081-0/+1
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* vhdl: renames iirs_walk to vhdl-nodes_walkTristan Gingold2019-05-081-1/+1
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* vhdl: move iirs_utils to vhdl.utilsTristan Gingold2019-05-061-1/+1
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* vhdl: move disp_tree and disp_vhdl as vhdl child.Tristan Gingold2019-05-041-2/+2
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* Rework list implementation, use iterator.Tristan Gingold2017-11-111-8/+10
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* Create default value for ports.Tristan Gingold2017-05-091-2/+1
| | | | Fix #328
* vhdl08: allow unaffected in sequential signal assignments.Tristan Gingold2016-11-011-15/+52
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* Add translation for selected signal assignment.Tristan Gingold2016-11-011-2/+26
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* canon: do not set formal of association by position.Tristan Gingold2016-10-191-8/+2
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* Rewrite most of error and warning messages.Tristan Gingold2016-08-021-2/+4
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* Add support for conditional assignments.Tristan Gingold2016-01-161-12/+27
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* Move translate and simulate.Tristan Gingold2014-11-051-0/+182