iCE40/ghdl - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	vhdl: parse verification unit (WIP).	Tristan Gingold	2019-08-17	1	-0/+2
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*	vhdl: declare verification units (WIP).	Tristan Gingold	2019-08-16	1	-0/+6
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*	Add support for PSL assumptions, used in formal verification (#880)	Pepijn de Vos	2019-08-07	1	-1/+3
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	* vhdl: make the parser understand PSL assume * assume does not actually have report according to the spec. Just a property. * add SPL assume to semantic analysis * canonicalise PSL assume * add assume to annotations * add PSL assume to simulation code * statement -> directive * add assume to translation files * update ticked24 testcase * correctly parse assume * add assume testcase * refactor chunk of duplicated code
*	vhdl: rename Cover_Statement to Cover_Directive.	Tristan Gingold	2019-07-04	1	-1/+1
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*	vhdl: parse and analyze restrict directive.	Tristan Gingold	2019-07-04	1	-0/+2
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*	vhdl: add anonymous_signal_declaration.	Tristan Gingold	2019-07-03	1	-0/+3
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*	vhdl: improve error messages for generate statement.	Tristan Gingold	2019-06-12	1	-1/+1
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*	vhdl-errors: avoid a crash on error type.	Tristan Gingold	2019-06-05	1	-0/+3
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*	errorout: add messages group instead of continuation.	Tristan Gingold	2019-05-12	1	-15/+10
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*	vhdl: minor reformating.	Tristan Gingold	2019-05-11	1	-4/+3
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*	vhdl: decouple errorouts a bit more.	Tristan Gingold	2019-05-10	1	-8/+13
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*	vhdl: replace Iir_Int64 by Int64, and Iir_Fp64 by Fp64.	Tristan Gingold	2019-05-10	1	-3/+3
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*	Extract psl-errors from errorout.	Tristan Gingold	2019-05-10	1	-5/+0
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*	vhdl: extract vhdl.errors from errorout.	Tristan Gingold	2019-05-08	1	-0/+990