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* types: introduce Direction_Type, which replaces Iir_Direction.Tristan Gingold2020-04-201-8/+2
| | | | Global renaming.
* vhdl: handling attribute specification in instantiations. Fix #1229Tristan Gingold2020-04-161-3/+3
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* synth-oper: recognize more operations from std_logic_arith.Tristan Gingold2020-04-121-0/+26
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* vhdl: recognize math_real.floor. For #1210Tristan Gingold2020-04-111-0/+1
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* vhdl: recognize ext/sxt from std_logic_arith.Tristan Gingold2020-04-111-0/+3
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* vhdl: recognize comparaison of std_logic_arith.Tristan Gingold2020-04-111-0/+54
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* vhdl: add scalar_size. Size of scalar types is computed during analysis.Tristan Gingold2020-04-061-1/+24
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* vhdl: recognize reduce functions in std_logic_misc.Tristan Gingold2020-03-281-1/+15
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* vhdl: move get_subprogram_body_origin to vhdl-sem_inst.Tristan Gingold2020-03-241-0/+11
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* synth: handle ieee.numeric_std.to_01Tristan Gingold2020-03-221-0/+3
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* vhdl: recognize minimum/maximum in numeric_std. For #1168Tristan Gingold2020-03-211-0/+14
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* synth: handle more operations from synsopsys packages.Tristan Gingold2020-03-141-8/+12
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* vhdl: recognize more std_logic_arith operations.Tristan Gingold2020-03-131-1/+37
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* vhdl-ieee-std_logic_arith: recognize more conversions.Tristan Gingold2020-03-111-1/+6
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* vhdl: recognize mod/rem operators.Tristan Gingold2020-03-101-0/+14
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* synthesis: add option --vendor-library= for synthesis.Tristan Gingold2020-03-101-0/+9
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* vhdl: recognize conversion functions from std_logic_1164Tristan Gingold2020-02-181-0/+6
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* synth: handle some rotation and shifts. Fix #1077Tristan Gingold2020-01-301-0/+5
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* synth: handle matching comparisons. Fix #1109Tristan Gingold2020-01-241-0/+42
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* synth: add id_abs gate. For #1101Tristan Gingold2020-01-201-0/+2
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* synth: handle more signed operations. For #1101Tristan Gingold2020-01-191-0/+4
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* vhdl: recognize predefined shift operators for ieee.numeric_std. For #1077Tristan Gingold2020-01-111-0/+9
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* synth: handle ieee.math_real.round Fix #1075Tristan Gingold2020-01-101-0/+1
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* ams-vhdl: add support for 'delayed for quantity.Tristan Gingold2019-12-311-0/+4
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* ams-vhdl: handle zoh, ltf and ztf attributes.Tristan Gingold2019-12-311-0/+25
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* ams-vhdl: add simultaneous null statement.Tristan Gingold2019-12-301-0/+39
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* ams-vhdl: add frequency function, minor fixes.Tristan Gingold2019-12-301-0/+1
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* ams-vhdl: improve error recoveryTristan Gingold2019-12-301-0/+1
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* ams-vhdl: analyze, canon and print simultaneous procedural statements.Tristan Gingold2019-12-301-2/+7
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* ams-vhdl: fix tree consistency for terminal declaration.Tristan Gingold2019-12-301-2/+2
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* ams-vhdl: check nature for record natures and terminals.Tristan Gingold2019-12-301-1/+15
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* vhdl-ams: fix tree consistency for subnature declaration.Tristan Gingold2019-12-291-4/+4
| | | | Also fix use and canon for it.
* vhdl-ams: fix overload for simple simultaneous statement.Tristan Gingold2019-12-291-0/+4
| | | | Fix tree consistency for branch quantity declarations.
* vhdl: improve support of AMS-vhdl (array and record natures, source quantities)Tristan Gingold2019-12-281-28/+643
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* vhdl: add Has_Delay_Machanism for optional 'inertial' printing.Tristan Gingold2019-12-261-0/+11
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* vhdl: recognize ieee.std_logic_1164.is_x.Tristan Gingold2019-12-241-0/+3
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* vhdl: recognize sin and cos from math_real.Tristan Gingold2019-11-261-0/+2
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* synth: preliminary work to support intrinsic procedures.Tristan Gingold2019-11-141-0/+5
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* vhdl: recognize rising_edge/falling_edge.Tristan Gingold2019-11-061-0/+3
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* vhdl: allow attributes in vunit declarations.Tristan Gingold2019-10-301-0/+2
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* vhdl: recognize std_logic_unsigned.conv_integer.Tristan Gingold2019-10-131-0/+2
| | | | Handle more operators in synth.
* vhdl: recognize conv_integer functions from std_logic_arith.Tristan Gingold2019-10-111-1/+6
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* vhdl: recognize std_logic_signed package (from synopsys).Tristan Gingold2019-10-111-0/+13
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* vhdl: recognize minus from std_logic_unsignedTristan Gingold2019-10-111-0/+6
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* vhdl: recognize conv_unsigned from ieee.std_logic_arith.Tristan Gingold2019-10-101-1/+7
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* synth: handle package bodies.Tristan Gingold2019-10-071-0/+1
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* vhdl: recognize to_bitvector.Tristan Gingold2019-10-071-0/+2
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* vhdl: recognize div operators.Tristan Gingold2019-09-301-0/+7
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* vhdl: recognize rotate functions.Tristan Gingold2019-09-221-0/+5
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* vhdl: add exit/next flags.Tristan Gingold2019-09-181-0/+22
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