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* update license headersumarcor2021-01-141-11/+9
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* vhdl: fix reprint of vhdl08 array element constraints.Tristan Gingold2021-01-051-255/+285
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* vhdl: handle locally static attributes on entity/architecture/configurationsTristan Gingold2020-12-081-266/+283
| | | | | | | | | | | | | Attributes of entity/architecture/configurations are expected to be locally static so that they can be referenced from outside (so on the non-instantiated entity). But many designs break this assumption. In relaxed mode, non-locally static attributes are allowed but now cannot be referenced outside the entity. Locally static attributes can be referenced from outside. Fix #1528
* vhdl: analyze subprogram instantiations. WIP. For #1470Tristan Gingold2020-09-261-203/+215
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* vhdl: parse subprogram instantiations. For #1470Tristan Gingold2020-09-241-201/+259
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* vhdl: parse and analyze force/release signal assignment statements.Tristan Gingold2020-08-011-85/+189
| | | | For #1416
* vhdl: adjust hanlding of guard signals for translate.Tristan Gingold2020-07-251-191/+193
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* vhdl: replace base_type with parent_type in nodesTristan Gingold2020-07-221-355/+329
| | | | | Only for subtype definition and remove base_type in type definitions. Allows to better track the addition of contraints.
* vhdl: fix ownership for recors subtypes.Tristan Gingold2020-07-181-269/+273
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* vhdl-nodes: make Subtype_Indication Maybe_Ref. For #641Tristan Gingold2020-06-301-221/+241
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* vhdl-nodes: add Open_Flag to all generic interfaces.Tristan Gingold2020-06-261-189/+204
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* vhdl: create default configuration for a vunit. Fix #1372Tristan Gingold2020-06-151-226/+251
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* Synthesis of PSL prev function.Tristan Gingold2020-06-021-132/+140
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* vhdl: parse PSL prev/stable/rose/fell builtin calls. For #662Tristan Gingold2020-06-021-115/+214
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* vhdl-nodes: use a flag field for direction.Tristan Gingold2020-05-201-1/+1
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* vhdl: allow attribute specifications in protected types. For #1252Tristan Gingold2020-04-201-252/+256
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* types: introduce Direction_Type, which replaces Iir_Direction.Tristan Gingold2020-04-201-25/+25
| | | | Global renaming.
* vhdl: add scalar_size. Size of scalar types is computed during analysis.Tristan Gingold2020-04-061-240/+286
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* synthesis: add option --vendor-library= for synthesis.Tristan Gingold2020-03-101-210/+225
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* ams-vhdl: add support for 'delayed for quantity.Tristan Gingold2019-12-311-25/+45
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* ams-vhdl: handle zoh, ltf and ztf attributes.Tristan Gingold2019-12-311-29/+119
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* ams-vhdl: add simultaneous null statement.Tristan Gingold2019-12-301-87/+123
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* ams-vhdl: improve error recoveryTristan Gingold2019-12-301-1/+2
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* ams-vhdl: analyze, canon and print simultaneous procedural statements.Tristan Gingold2019-12-301-86/+92
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* ams-vhdl: fix tree consistency for terminal declaration.Tristan Gingold2019-12-301-1/+1
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* ams-vhdl: check nature for record natures and terminals.Tristan Gingold2019-12-301-225/+247
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* vhdl-ams: fix tree consistency for subnature declaration.Tristan Gingold2019-12-291-1/+1
| | | | Also fix use and canon for it.
* vhdl: improve support of AMS-vhdl (array and record natures, source quantities)Tristan Gingold2019-12-281-379/+1315
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* vhdl: add Has_Delay_Machanism for optional 'inertial' printing.Tristan Gingold2019-12-261-91/+121
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* vhdl: allow attributes in vunit declarations.Tristan Gingold2019-10-301-197/+203
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* vhdl: add exit/next flags.Tristan Gingold2019-09-181-63/+107
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* vhdl: renames Conditional_Expression to Conditional_Expression_Chain.Tristan Gingold2019-09-021-11/+11
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* synth: handle verification units.Tristan Gingold2019-08-201-202/+226
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* vhdl: parse verification unit (WIP).Tristan Gingold2019-08-171-243/+256
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* vhdl: declare verification units (WIP).Tristan Gingold2019-08-161-263/+392
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* vhdl: improve reprint of inertial association.Tristan Gingold2019-08-111-152/+156
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* vhdl: remove unused Get/Set_Choice_Order.Tristan Gingold2019-08-091-275/+247
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* vhdl: remove severity from cover, report and severity from assume.Tristan Gingold2019-08-081-84/+86
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* vhdl-nodes: gather PSL nodes, regenerate nodes_meta.Tristan Gingold2019-08-071-95/+87
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* Add support for PSL assumptions, used in formal verification (#880)Pepijn de Vos2019-08-071-101/+137
| | | | | | | | | | | | | | | | | | | | | | | | | | * vhdl: make the parser understand PSL assume * assume does not actually have report according to the spec. Just a property. * add SPL assume to semantic analysis * canonicalise PSL assume * add assume to annotations * add PSL assume to simulation code * statement -> directive * add assume to translation files * update ticked24 testcase * correctly parse assume * add assume testcase * refactor chunk of duplicated code
* vhdl: linearize analyze and evaluation of concat operators.Tristan Gingold2019-07-261-1/+13
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* vhdl: rename Cover_Statement to Cover_Directive.Tristan Gingold2019-07-041-18/+18
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* vhdl: parse and analyze restrict directive.Tristan Gingold2019-07-041-89/+121
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* vhdl: add anonymous_signal_declaration.Tristan Gingold2019-07-031-151/+173
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* vhdl-disp_vhdl: print literals and identifiers from the source.Tristan Gingold2019-05-291-264/+292
| | | | Add Literal_Length and set it in the parser.
* vhdl: get rid of Get/Set_Physical_Unit.Tristan Gingold2019-05-281-280/+258
| | | | Use integer_literal for evaluated physical literals.
* vhdl: update AMS parsing.Tristan Gingold2019-05-241-172/+176
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* vhdl-parse: Add Has_Is for block_statement.Tristan Gingold2019-05-241-1/+3
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* vhdl-nodes: make subtype_Definition like the others.Tristan Gingold2019-05-231-201/+205
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* vhdl-nodes: fix minor typo.Tristan Gingold2019-05-111-54/+50
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