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* vhdl: add exit/next flags.Tristan Gingold2019-09-181-63/+107
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* vhdl: renames Conditional_Expression to Conditional_Expression_Chain.Tristan Gingold2019-09-021-11/+11
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* synth: handle verification units.Tristan Gingold2019-08-201-202/+226
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* vhdl: parse verification unit (WIP).Tristan Gingold2019-08-171-243/+256
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* vhdl: declare verification units (WIP).Tristan Gingold2019-08-161-263/+392
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* vhdl: improve reprint of inertial association.Tristan Gingold2019-08-111-152/+156
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* vhdl: remove unused Get/Set_Choice_Order.Tristan Gingold2019-08-091-275/+247
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* vhdl: remove severity from cover, report and severity from assume.Tristan Gingold2019-08-081-84/+86
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* vhdl-nodes: gather PSL nodes, regenerate nodes_meta.Tristan Gingold2019-08-071-95/+87
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* Add support for PSL assumptions, used in formal verification (#880)Pepijn de Vos2019-08-071-101/+137
| | | | | | | | | | | | | | | | | | | | | | | | | | * vhdl: make the parser understand PSL assume * assume does not actually have report according to the spec. Just a property. * add SPL assume to semantic analysis * canonicalise PSL assume * add assume to annotations * add PSL assume to simulation code * statement -> directive * add assume to translation files * update ticked24 testcase * correctly parse assume * add assume testcase * refactor chunk of duplicated code
* vhdl: linearize analyze and evaluation of concat operators.Tristan Gingold2019-07-261-1/+13
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* vhdl: rename Cover_Statement to Cover_Directive.Tristan Gingold2019-07-041-18/+18
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* vhdl: parse and analyze restrict directive.Tristan Gingold2019-07-041-89/+121
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* vhdl: add anonymous_signal_declaration.Tristan Gingold2019-07-031-151/+173
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* vhdl-disp_vhdl: print literals and identifiers from the source.Tristan Gingold2019-05-291-264/+292
| | | | Add Literal_Length and set it in the parser.
* vhdl: get rid of Get/Set_Physical_Unit.Tristan Gingold2019-05-281-280/+258
| | | | Use integer_literal for evaluated physical literals.
* vhdl: update AMS parsing.Tristan Gingold2019-05-241-172/+176
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* vhdl-parse: Add Has_Is for block_statement.Tristan Gingold2019-05-241-1/+3
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* vhdl-nodes: make subtype_Definition like the others.Tristan Gingold2019-05-231-201/+205
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* vhdl-nodes: fix minor typo.Tristan Gingold2019-05-111-54/+50
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* vhdl: replace Iir_Int64 by Int64, and Iir_Fp64 by Fp64.Tristan Gingold2019-05-101-50/+50
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* vhdl: move nodes_meta package to vhdl child.Tristan Gingold2019-05-061-0/+10786