Commit message (Collapse) | Author | Age | Files | Lines | |
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* | types: introduce Direction_Type, which replaces Iir_Direction. | Tristan Gingold | 2020-04-20 | 1 | -1/+1 |
| | | | | Global renaming. | ||||
* | vhdl-prints: handle evaluated expression for qualified_expression. | Tristan Gingold | 2020-04-18 | 1 | -16/+19 |
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* | psl: keep denoting names in the PSL ast. | Tristan Gingold | 2020-03-13 | 1 | -1/+2 |
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* | vhdl-prints: disable code to display anonymous signal. | Tristan Gingold | 2020-03-02 | 1 | -2/+10 |
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* | ams-vhdl: add support for 'delayed for quantity. | Tristan Gingold | 2019-12-31 | 1 | -0/+2 |
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* | ams-vhdl: handle zoh, ltf and ztf attributes. | Tristan Gingold | 2019-12-31 | 1 | -8/+7 |
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* | ams-vhdl: add simultaneous null statement. | Tristan Gingold | 2019-12-30 | 1 | -40/+89 |
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* | ams-vhdl: handle record nature end name. | Tristan Gingold | 2019-12-30 | 1 | -0/+2 |
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* | ams-vhdl: analyze, canon and print simultaneous procedural statements. | Tristan Gingold | 2019-12-30 | 1 | -1/+36 |
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* | ams-vhdl: print subnature declarations. | Tristan Gingold | 2019-12-30 | 1 | -1/+16 |
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* | vhdl: improve support of AMS-vhdl (array and record natures, source quantities) | Tristan Gingold | 2019-12-28 | 1 | -127/+405 |
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* | vhdl: add Has_Delay_Machanism for optional 'inertial' printing. | Tristan Gingold | 2019-12-26 | 1 | -0/+2 |
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* | vhdl-prints: subtype indication is optional in object alias. | Tristan Gingold | 2019-12-26 | 1 | -3/+2 |
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* | vhdl-prints: handle more constructs in psl vunit. | Tristan Gingold | 2019-10-31 | 1 | -0/+5 |
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* | vhdl-prints: do not crash on vunit declarations. | Tristan Gingold | 2019-10-23 | 1 | -0/+4 |
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* | psl: add active state. | Tristan Gingold | 2019-10-21 | 1 | -0/+7 |
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* | vhdl-prints: handle restrict in vunit. | Tristan Gingold | 2019-10-21 | 1 | -0/+2 |
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* | vhdl-prints: add parenthesis around boolean and/or. | Tristan Gingold | 2019-10-18 | 1 | -0/+4 |
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* | vhdl: renames Conditional_Expression to Conditional_Expression_Chain. | Tristan Gingold | 2019-09-02 | 1 | -3/+4 |
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* | vhdl psl: fully scan PSL keywords in scanner. | Tristan Gingold | 2019-08-20 | 1 | -1/+1 |
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* | vhdl-prints: handle architecture in verification unit hierarchical name. | Tristan Gingold | 2019-08-20 | 1 | -0/+7 |
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* | vhdl-prints: handle verification units. | Tristan Gingold | 2019-08-20 | 1 | -318/+354 |
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* | vhdl: declare verification units (WIP). | Tristan Gingold | 2019-08-16 | 1 | -0/+13 |
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* | vhdl: add PSL keywords to vhdl08 reserved words. | Tristan Gingold | 2019-08-14 | 1 | -6/+6 |
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* | vhdl: improve reprint of inertial association. | Tristan Gingold | 2019-08-11 | 1 | -1/+5 |
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* | vhdl: handle subtype indication (with range) in discrete_range. | Tristan Gingold | 2019-08-10 | 1 | -0/+2 |
| | | | | For #877 | ||||
* | vhdl: remove severity from cover, report and severity from assume. | Tristan Gingold | 2019-08-08 | 1 | -5/+4 |
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* | Add support for PSL assumptions, used in formal verification (#880) | Pepijn de Vos | 2019-08-07 | 1 | -4/+24 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | * vhdl: make the parser understand PSL assume * assume does not actually have report according to the spec. Just a property. * add SPL assume to semantic analysis * canonicalise PSL assume * add assume to annotations * add PSL assume to simulation code * statement -> directive * add assume to translation files * update ticked24 testcase * correctly parse assume * add assume testcase * refactor chunk of duplicated code | ||||
* | vhdl-prints: improve output for ports/generics. | Tristan Gingold | 2019-07-22 | 1 | -5/+27 |
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* | vhdl: rename Cover_Statement to Cover_Directive. | Tristan Gingold | 2019-07-04 | 1 | -6/+6 |
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* | vhdl: parse and analyze restrict directive. | Tristan Gingold | 2019-07-04 | 1 | -1/+18 |
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* | vhdl: add anonymous_signal_declaration. | Tristan Gingold | 2019-07-03 | 1 | -0/+13 |
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* | vhdl-prints: try to print error content. | Tristan Gingold | 2019-06-04 | 1 | -0/+10 |
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* | vhdl-prints: fix extra 'else' in disp_conditional_waveform. | Tristan Gingold | 2019-06-03 | 1 | -2/+3 |
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* | vhdl-prints: improve indent. | Tristan Gingold | 2019-06-02 | 1 | -0/+4 |
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* | vhdl-prints: improve output for if/then, architecture. | Tristan Gingold | 2019-06-01 | 1 | -0/+4 |
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* | vhdl-formatters: add indent. | Tristan Gingold | 2019-06-01 | 1 | -1/+5 |
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* | vhdl-prints: handle PSL, add psl tokens for strong and inclusive variants. | Tristan Gingold | 2019-05-30 | 1 | -85/+394 |
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* | vhdl: renames disp_vhdl to prints | Tristan Gingold | 2019-05-30 | 1 | -0/+4155 |