| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | add synthesis support for logic operators on numeric types (#893) | Pepijn de Vos | 2019-08-15 | 2 | -0/+114 |
| | | | | | | | | | * add logic operators on unsigned * handle signed too * handle unary not | ||||
| * | vhdl: handle PSL keywords as vhdl08 reserved words; switch to PSL scanner mode. | Tristan Gingold | 2019-08-14 | 1 | -0/+9 |
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| * | vhdl: add PSL keywords to vhdl08 reserved words. | Tristan Gingold | 2019-08-14 | 7 | -78/+98 |
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| * | vhdl-nodes_walk: handle iir_kind_psl_default_clock. | Tristan Gingold | 2019-08-13 | 1 | -1/+2 |
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| * | libghdl: also add synthesis part. For #884 | Tristan Gingold | 2019-08-13 | 1 | -0/+2 |
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| * | libghdl: preliminary work to also support synth. | Tristan Gingold | 2019-08-13 | 2 | -4/+9 |
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| * | vhdl: improve reprint of inertial association. | Tristan Gingold | 2019-08-11 | 6 | -181/+206 |
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| * | vhdl-sem: fix minor thinko for sem_insert_anonymous_signal. | Tristan Gingold | 2019-08-11 | 1 | -1/+24 |
| | | | | | Fix #885 | ||||
| * | vhdl: avoid crash on incorrect unit name. | Tristan Gingold | 2019-08-10 | 2 | -6/+36 |
| | | | | | Fix #886 | ||||
| * | vhdl: handle subtype indication (with range) in discrete_range. | Tristan Gingold | 2019-08-10 | 7 | -63/+105 |
| | | | | | For #877 | ||||
| * | vhdl: remove unused Get/Set_Choice_Order. | Tristan Gingold | 2019-08-09 | 5 | -304/+247 |
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| * | vhdl: remove -Whides warnings for processes without a label. | Tristan Gingold | 2019-08-08 | 1 | -0/+9 |
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| * | vhdl: remove severity from cover, report and severity from assume. | Tristan Gingold | 2019-08-08 | 9 | -131/+154 |
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| * | vhdl-nodes: gather PSL nodes, regenerate nodes_meta. | Tristan Gingold | 2019-08-07 | 2 | -125/+91 |
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| * | Add support for PSL assumptions, used in formal verification (#880) | Pepijn de Vos | 2019-08-07 | 23 | -141/+293 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | * vhdl: make the parser understand PSL assume * assume does not actually have report according to the spec. Just a property. * add SPL assume to semantic analysis * canonicalise PSL assume * add assume to annotations * add PSL assume to simulation code * statement -> directive * add assume to translation files * update ticked24 testcase * correctly parse assume * add assume testcase * refactor chunk of duplicated code | ||||
| * | vhdl: allow discrete subtype indication for discrete_range. | Tristan Gingold | 2019-08-06 | 5 | -45/+53 |
| | | | | | For #877 | ||||
| * | vhdl: for time resolution, do not consider unit name from textio body. | Tristan Gingold | 2019-08-06 | 2 | -10/+38 |
| | | | | | For #881 | ||||
| * | synth: improve support of vhdl08. Fix #882 | Tristan Gingold | 2019-08-05 | 1 | -1/+9 |
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| * | synth: add support for memories. | Tristan Gingold | 2019-07-29 | 1 | -0/+2 |
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| * | synth: unconstrained arrays. | Tristan Gingold | 2019-07-28 | 1 | -0/+3 |
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| * | synth: preliminary support of dynamic indexing. | Tristan Gingold | 2019-07-28 | 2 | -47/+70 |
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| * | vhdl: linearize analyze and evaluation of concat operators. | Tristan Gingold | 2019-07-26 | 5 | -360/+647 |
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| * | vhdl+synth: recognize /= to std_logic_unsigned. | Tristan Gingold | 2019-07-25 | 2 | -1/+13 |
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| * | vhdl: handle (discard) more pragmas. | Tristan Gingold | 2019-07-25 | 1 | -0/+8 |
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| * | vhdl annotations: fix annotation of type in interface list. | Tristan Gingold | 2019-07-24 | 1 | -0/+1 |
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| * | vhdl scanner: handle pragma translate_on/translate_off. | Tristan Gingold | 2019-07-24 | 2 | -4/+98 |
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| * | vhdl: recognize resize function. | Tristan Gingold | 2019-07-24 | 2 | -0/+38 |
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| * | vhdl-prints: improve output for ports/generics. | Tristan Gingold | 2019-07-22 | 1 | -5/+27 |
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| * | synth: minor rework. | Tristan Gingold | 2019-07-22 | 2 | -0/+14 |
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| * | synth: initial support for for-generate statement. | Tristan Gingold | 2019-07-20 | 1 | -5/+8 |
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| * | vhdl: add a comment. | Tristan Gingold | 2019-07-16 | 1 | -0/+3 |
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| * | synth: add > and >= operators (#870) | Pepijn de Vos | 2019-07-16 | 2 | -0/+68 |
| | | | | | | | * synth: add > and >= operators * synth: update ghdlsynth_gates.h | ||||
| * | vhdl: avoid a crash on no matching operator error. | Tristan Gingold | 2019-07-15 | 1 | -1/+7 |
| | | | | | Fix #869 | ||||
| * | vhdl-sem_names: avoid a crash on parenthesis of | Tristan Gingold | 2019-07-15 | 1 | -2/+2 |
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| * | find_top_entity: avoid crash on missing entity, handle | Tristan Gingold | 2019-07-15 | 2 | -13/+27 |
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| * | ghdlsynth: check top entity can be a top entity. | Tristan Gingold | 2019-07-14 | 3 | -4/+6 |
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| * | vhdl: refactoring: remove configure function with string access. | Tristan Gingold | 2019-07-14 | 4 | -29/+14 |
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| * | vhdl: set location on reference to the anonymous signal declaration. | Tristan Gingold | 2019-07-14 | 1 | -0/+1 |
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| * | vhdl: fixes in find_top_entity (handle for-generate, remove early return) | Tristan Gingold | 2019-07-14 | 2 | -5/+27 |
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| * | vhdl: cleanup in clear_instantiation_configuration. | Tristan Gingold | 2019-07-13 | 4 | -70/+23 |
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| * | simul-elaboration: rewrite assertion. | Tristan Gingold | 2019-07-13 | 1 | -3/+3 |
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| * | vhdl-configuration: improve error message. | Tristan Gingold | 2019-07-11 | 1 | -1/+1 |
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| * | vhdl: minor reformating. | Tristan Gingold | 2019-07-11 | 2 | -8/+5 |
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| * | vhdl-sem_lib: save and restore nbr_errors in | Tristan Gingold | 2019-07-11 | 1 | -0/+10 |
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| * | libghdl: import Free_Dependence_List. | Tristan Gingold | 2019-07-11 | 2 | -0/+4 |
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| * | vhdl-nodes: add comments | Tristan Gingold | 2019-07-11 | 1 | -0/+16 |
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| * | synth: do not crash on use of std_logic_1164 2008. | Tristan Gingold | 2019-07-10 | 1 | -10/+4 |
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| * | vhdl: improve an error message. | Tristan Gingold | 2019-07-10 | 1 | -1/+1 |
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| * | vhdl-sem_lib: Load_Parse_Design_Unit: ignore checksum if | Tristan Gingold | 2019-07-09 | 1 | -3/+6 |
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| * | vhdl-sem_lib: free_dependencies: only free entity aspect. | Tristan Gingold | 2019-07-09 | 1 | -3/+19 |
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