iCE40/ghdl - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Handle default parameters for file_open.	Tristan Gingold	2016-06-02	4	-7/+22
\| \| \| \|	Display backtrace for error in file_open.
*	Remove Get/Set_Type_Reference	Tristan Gingold	2016-06-01	6	-217/+166
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*	vhdl2008: implement new 'use clause' rules for types.	Tristan Gingold	2016-05-31	10	-231/+444
\| \| \| \|	Adjust test issue72.
*	Individual association: fix crash for array conversion due to slice.	Tristan Gingold	2016-05-27	1	-0/+6
\| \| \| \|	Fix for issue73.
*	Minor cleanup.	Tristan Gingold	2016-03-31	1	-9/+0
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*	simulation: remove unused kind_range.	Tristan Gingold	2016-03-29	2	-9/+1
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*	Avoid a crash on error.	Tristan Gingold	2016-03-26	5	-91/+73
\| \| \| \|	Fix bug041.
*	Adjust previous patch (detect incorrect use of PSL endpoint in expressions)	Tristan Gingold	2016-03-23	3	-167/+171
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*	PSL: add clocked SERE, make endpoints visible from VHDL.	Tristan Gingold	2016-03-22	17	-237/+423
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*	Create psl_endpoint_declaration.	Tristan Gingold	2016-03-20	4	-169/+226
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*	wip.	Tristan Gingold	2016-03-20	1	-1/+3
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*	PSL: add counters, generate rti and add --psl-report	Tristan Gingold	2016-03-18	4	-57/+66
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*	PSL translate: handle bit type.	Tristan Gingold	2016-03-18	1	-4/+8
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*	translation: avoid memory leak while allocating ports.	Tristan Gingold	2016-03-16	4	-18/+36
\| \| \| \|	Issue found in bug040.
*	trans-chap12: extract gen_stubs from write_list_list.	Tristan Gingold	2016-03-11	2	-13/+54
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*	simulation: reuse Mode_Signal_Type from grt.types.	Tristan Gingold	2016-03-10	5	-72/+76
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*	elaboration: use std_time to represent time in signal table.	Tristan Gingold	2016-03-10	3	-9/+9
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*	simulation: add block id.	Tristan Gingold	2016-03-10	3	-1/+13
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*	simul debugger: display packages and configuration.	Tristan Gingold	2016-03-10	1	-2/+12
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*	trans-chap12: refactor.	Tristan Gingold	2016-03-07	2	-53/+70
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*	translate: separate decl and stmt elab subprograms.	Tristan Gingold	2016-02-23	6	-96/+319
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*	translate: minor reformating.	Tristan Gingold	2016-02-21	1	-24/+19
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*	grt: remove rti field in signals (to reduce space).	Tristan Gingold	2016-02-21	1	-1/+0
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*	ortho: rename start/finish_const_value to start/finish_init_value.	Tristan Gingold	2016-02-21	8	-64/+64
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*	trans-chap12: factorize code.	Tristan Gingold	2016-02-20	1	-9/+1
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*	Refactoring in simulate in order to link with ortho.	Tristan Gingold	2016-02-20	16	-1213/+1307
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*	parse: detect early use of signature in expressions.	Tristan Gingold	2016-02-18	1	-1/+8
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*	parse: avoid weird error message for end protected.	Tristan Gingold	2016-02-17	1	-1/+8
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*	assocations: check rules for unconstrained formal (LRM08 5.3.2.2 e 3)	Tristan Gingold	2016-02-17	2	-4/+39
\| \| \| \|	Fix issue40
*	Tentative fix for issue43.	Tristan Gingold	2016-02-17	1	-1/+1
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*	Fix crash of issue42.	Tristan Gingold	2016-02-17	1	-1/+2
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*	simul debugger: add info instances	Tristan Gingold	2016-02-17	2	-3/+46
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*	psl: cover directive works on a sequence, not on a property.	Tristan Gingold	2016-02-17	1	-2/+0
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*	PSL: move canon code to canon.adb	Tristan Gingold	2016-02-17	1	-0/+2
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*	simul: fix local protected object, boolean for-generate loop	Tristan Gingold	2016-02-14	3	-38/+51
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*	simul debugger: handle more concurrent statements.	Tristan Gingold	2016-02-14	1	-0/+50
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*	simul: more fixes for std_ulogic.	Tristan Gingold	2016-02-14	2	-17/+21
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*	psl: cover directive works on a sequence, not on a property.	Tristan Gingold	2016-02-14	16	-78/+292
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*	simul: preliminary work to support PSL.	Tristan Gingold	2016-02-14	7	-105/+323
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*	PSL: move canon code to canon.adb	Tristan Gingold	2016-02-14	7	-135/+308
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*	simul: return the exit status set by std.env	Tristan Gingold	2016-02-14	1	-2/+4
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*	simul: check for no unconstrained port/generic of top-level entity.	Tristan Gingold	2016-02-14	2	-1/+30
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*	simul: make delayed signal elaborated.	Tristan Gingold	2016-02-10	1	-0/+1
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*	simul: add support of e8.	Tristan Gingold	2016-02-10	9	-170/+205
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*	simul: handle generic override.	Tristan Gingold	2016-02-10	3	-20/+106
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*	evaluation: handle whitespace for 'value.	Tristan Gingold	2016-02-10	3	-1/+54
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*	build_enumeration_value: correctly handle characters.	Tristan Gingold	2016-02-10	1	-12/+22
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*	simul: handle slice in individual association for subprograms.	Tristan Gingold	2016-02-10	1	-0/+11
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*	simul: fix type conversion to unconstrained array.	Tristan Gingold	2016-02-10	1	-14/+35
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*	simul: fix corner cases for image.	Tristan Gingold	2016-02-10	1	-100/+131
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