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* vhdl-parse: handle inside commentsTristan Gingold2022-11-211-0/+31
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* vhdl-prints: add an option to display commentsTristan Gingold2022-11-203-3/+74
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* pyGHDL: add file_comments.pyTristan Gingold2022-11-204-2/+42
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* Add an API to gather comments.Tristan Gingold2022-11-207-4/+380
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* grt-algos: clarify the APITristan Gingold2022-11-203-6/+11
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* vhdl-evaluation(build_array_choices_vector): handle vhdl-08 aggregates.Tristan Gingold2022-11-163-47/+61
| | | | For #2244
* vhdl-sem_expr: fix aggregate index for vhdl-08Tristan Gingold2022-11-161-13/+42
| | | | | When the index direction is determined by the direction of range choices. Fix #2244
* synth: improve error message for ghdl/ghdl-yosys-plugin#179Tristan Gingold2022-11-151-1/+3
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* synth: avoid a crash on signal assignment in non-sensitized process.Tristan Gingold2022-11-141-2/+9
| | | | Fix ghdl/ghdl-yosys-plugin#180
* Remove trailing spacesTristan Gingold2022-11-082-2/+2
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* elab-vhdl_expr: fix a crash on simple aggregates. Fix #2240Tristan Gingold2022-11-082-15/+13
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* vhdl: fix some compiler warningsTristan Gingold2022-11-083-6/+2
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* vhdl-sem_expr: fix a crash after error. Fix #2239Tristan Gingold2022-11-081-0/+2
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* Added id to warnings related to attributes. (#2242)cderrien2022-11-085-2/+25
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* Escape port name in dot output. (#2241)cderrien2022-11-081-1/+1
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* vhdl/translate: handle predefined operators as conversion functionsTristan Gingold2022-11-073-44/+73
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* netlists-memories: refactoringTristan Gingold2022-11-061-113/+105
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* netlists-memories: factorize code.Tristan Gingold2022-11-061-83/+41
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* netlists: factorize codeTristan Gingold2022-11-061-100/+56
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* synth-environment.adb: fix warningTristan Gingold2022-11-051-1/+0
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* synth: rework memory inference. Fix #2232Tristan Gingold2022-11-053-78/+233
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* netlists-builders: allow building mem_wr_sync without clk and en.Tristan Gingold2022-11-051-4/+10
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* synth: infere a dff (instead of an idff) when the init value is XTristan Gingold2022-11-032-6/+21
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* vhdl-sem_expr(sem_qualified_expression): relax staticness rules.Tristan Gingold2022-11-021-1/+11
| | | | Fix #2238
* synth: handle bit/unsigned and bit/signed vhdl 08 operators.Tristan Gingold2022-11-021-12/+36
| | | | Fix #2237
* Add missing -g for generic override to CLI help for RUNOPTS (#2220)svnesbo2022-11-011-0/+1
| | | Co-authored-by: Simon Voigt Nesbo <Simon.Voigt.Nesbo@hvl.no>
* netlists-inference: handle flip-flop with different patterns.Tristan Gingold2022-10-301-23/+75
| | | | Fix #2231
* netlists-gates: add a commentTristan Gingold2022-10-301-0/+1
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* vhdl-sem_names(sem_name_free): handle iir_kind_slice_name. For #2233Tristan Gingold2022-10-291-0/+1
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* vhdl-evaluation: handle to_string_digits. For #2233Tristan Gingold2022-10-291-5/+50
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* synth: internal refactoringTristan Gingold2022-10-294-121/+93
| | | | use memtyp for eval_static_predefined_function_call
* elab-vhdl_types: abstract elab_floating_type_definitionTristan Gingold2022-10-291-10/+15
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* synth: fix crash in disp_verilog. Fix #2234Tristan Gingold2022-10-291-3/+8
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* synth: handle copyback associations in any order.Tristan Gingold2022-10-191-12/+30
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* synth-vhdl_eval: handle std_logic_misc reduce functionsTristan Gingold2022-10-191-0/+27
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* synth-vhdl_oper: handle xor/nand/nor/xnor reduce from std_logic_miscTristan Gingold2022-10-191-16/+34
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* synth-vhdl_oper: handle and_reduce. Fix #2224Tristan Gingold2022-10-191-1/+10
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* synth: extract elab-vhdl_utils from synth-vhdl_stmts.Tristan Gingold2022-10-183-142/+241
| | | | Fix #2222
* vhdl-sem_assocs: handle association with external signal names.Tristan Gingold2022-10-184-63/+77
| | | | Fix #2221
* win64: fix FP argument passingTristan Gingold2022-10-171-2/+8
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* vhdl-sem_expr.adb: avoid crash after error on aggregate. Fix #2218Tristan Gingold2022-10-161-0/+6
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* vhdl-sem_expr.adb(is_string_type): check character type.Tristan Gingold2022-10-161-1/+3
| | | | Fix #2217
* vhdl-parse.adb: handle external names as assignment target.Tristan Gingold2022-10-141-2/+4
| | | | Fix #2219
* synth: handle record conversionTristan Gingold2022-10-141-0/+3
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* synth-vhdl_expr: support alias in indexed namesTristan Gingold2022-10-141-1/+2
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* synth: avoid extra conversion during alias elaborationTristan Gingold2022-10-141-6/+4
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* simul: fix spurious error about multiple driversTristan Gingold2022-10-141-0/+2
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* simul: handle delayed attributeTristan Gingold2022-10-142-6/+66
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* synth: handle alias of access objects.Tristan Gingold2022-10-131-1/+1
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* simul: handle last_event and last_activeTristan Gingold2022-10-133-4/+114
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