iCE40/ghdl - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	vhdl-nodes: gather PSL nodes, regenerate nodes_meta.	Tristan Gingold	2019-08-07	2	-125/+91
\|
*	Add support for PSL assumptions, used in formal verification (#880)	Pepijn de Vos	2019-08-07	30	-141/+334
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	* vhdl: make the parser understand PSL assume * assume does not actually have report according to the spec. Just a property. * add SPL assume to semantic analysis * canonicalise PSL assume * add assume to annotations * add PSL assume to simulation code * statement -> directive * add assume to translation files * update ticked24 testcase * correctly parse assume * add assume testcase * refactor chunk of duplicated code
*	vhdl: allow discrete subtype indication for discrete_range.	Tristan Gingold	2019-08-06	5	-45/+53
\| \| \| \|	For #877
*	vhdl: for time resolution, do not consider unit name from textio body.	Tristan Gingold	2019-08-06	2	-10/+38
\| \| \| \|	For #881
*	synth: improve support of vhdl08. Fix #882	Tristan Gingold	2019-08-05	2	-5/+22
\|
*	synth: add asserts in synth-values	Tristan Gingold	2019-08-05	1	-0/+5
\|
*	synth: handle subtype conversions.	Tristan Gingold	2019-08-05	5	-73/+154
\|
*	synth: handle signed conversions in disp_vhdl.	Tristan Gingold	2019-08-05	1	-2/+6
\|
*	synth: preliminary support of integer literals.	Tristan Gingold	2019-08-02	2	-18/+67
\|
*	synth: add a debug procedure.	Tristan Gingold	2019-08-02	2	-0/+22
\|
*	synth: improve error message for multiple assignments.	Tristan Gingold	2019-08-02	1	-4/+20
\|
*	synth: handle signed integer comparisons (#878)	Pepijn de Vos	2019-08-01	3	-0/+43
\| \| \| \| \| \| \| \| \| \|	* comparisons with integer literals * display signed comparison nicely * revert literal size changes * properly display signed values
*	synth: handle partial assignments in a process (WIP).	Tristan Gingold	2019-08-01	1	-18/+75
\|
*	synth: refactoring in inference/environment.	Tristan Gingold	2019-08-01	3	-7/+13
\|
*	synth: refactor inference, add comment, strengthen check.	Tristan Gingold	2019-08-01	4	-31/+62
\|
*	synth: refactoring in synth-inference.	Tristan Gingold	2019-07-31	1	-129/+137
\|
*	synth: add location on monadic operators.	Tristan Gingold	2019-07-31	1	-7/+10
\|
*	synth: regenerate ghdlsynth_gates.h	Tristan Gingold	2019-07-31	1	-3/+4
\|
*	synth: fix a crash in instantiation.	Tristan Gingold	2019-07-31	2	-8/+9
\|
*	synth: slightly improve output for indexes.	Tristan Gingold	2019-07-30	1	-3/+7
\|
*	synth: adjust output for dyn_insert, add dpram2 test.	Tristan Gingold	2019-07-30	1	-2/+2
\|
*	synth: fixes for indexed names.	Tristan Gingold	2019-07-30	3	-3/+13
\|
*	synth: rework indexed names.	Tristan Gingold	2019-07-30	4	-101/+106
\|
*	synth: handle more conversions in disp_vhdl	Tristan Gingold	2019-07-29	1	-1/+44
\|
*	synth: add support for memories.	Tristan Gingold	2019-07-29	15	-152/+445
\|
*	synth: remove extract_bound (trivial).	Tristan Gingold	2019-07-28	5	-15/+6
\|
*	synth: unconstrained arrays.	Tristan Gingold	2019-07-28	5	-17/+71
\|
*	synth: preliminary support of dynamic indexing.	Tristan Gingold	2019-07-28	13	-740/+956
\|
*	vhdl: linearize analyze and evaluation of concat operators.	Tristan Gingold	2019-07-26	5	-360/+647
\|
*	synth: rework range.	Tristan Gingold	2019-07-26	5	-48/+52
\|
*	synth: preliminary support of integer subtypes.	Tristan Gingold	2019-07-26	8	-42/+68
\|
*	synth: handle array aggregate.	Tristan Gingold	2019-07-26	2	-27/+32
\|
*	synth: handle bit.	Tristan Gingold	2019-07-25	3	-4/+11
\|
*	synth: array inequality, integer in choices.	Tristan Gingold	2019-07-25	2	-0/+11
\|
*	vhdl+synth: recognize /= to std_logic_unsigned.	Tristan Gingold	2019-07-25	3	-1/+16
\|
*	vhdl: handle (discard) more pragmas.	Tristan Gingold	2019-07-25	3	-1/+19
\|
*	synth: save and display locations for instances.	Tristan Gingold	2019-07-25	8	-66/+247
\|
*	synth: fix incorrect slice in disp_vhdl for Insert.	Tristan Gingold	2019-07-25	1	-6/+1
\|
*	vhdl annotations: fix annotation of type in interface list.	Tristan Gingold	2019-07-24	1	-0/+1
\|
*	synth: fix bad ordering in case statement.	Tristan Gingold	2019-07-24	1	-2/+3
\|
*	synth: do not consider (unrecognized) ieee functions as user functions.	Tristan Gingold	2019-07-24	1	-0/+19
\|
*	synth: enable handling of pragma translate_on/off.	Tristan Gingold	2019-07-24	1	-0/+3
\|
*	vhdl scanner: handle pragma translate_on/translate_off.	Tristan Gingold	2019-07-24	5	-5/+109
\|
*	synth: handle resize.	Tristan Gingold	2019-07-24	1	-0/+15
\|
*	synth: handle record type declarations.	Tristan Gingold	2019-07-24	1	-1/+11
\|
*	vhdl: recognize resize function.	Tristan Gingold	2019-07-24	4	-3/+43
\|
*	synth: fix slice/indexed assignment that partially override previous assign.	Tristan Gingold	2019-07-23	1	-5/+8
\|
*	synth: add more operators.	Tristan Gingold	2019-07-23	1	-1/+34
\|
*	synth: fix to_unsigned.	Tristan Gingold	2019-07-23	1	-2/+2
\|
*	synth: use original entity to display netlist.	Tristan Gingold	2019-07-23	7	-22/+314
\|