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* ghwdump should handle zero-length signals (#1327)Ben Reynwar2020-05-201-1/+1
| | | | | * Adding a test for issue #1326 to check that ghwdump doesn't crash with a zero-length signal. * Remove an assertion from ghwlib that prevents zero-length signals.
* synth-decls: handle unbounded record subtypes. Fix #1324Tristan Gingold2020-05-192-45/+28
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* vhdl-nodes: Rename and move shift/rotate predefined functions. Fix #1325Tristan Gingold2020-05-194-30/+27
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* netlists: initial infrastructure for attributes. For #1318Tristan Gingold2020-05-192-7/+62
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* WIP: netlists: reuse free instances.Tristan Gingold2020-05-181-37/+220
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* netlists: make free_instance private and remove_instance public.Tristan Gingold2020-05-181-6/+4
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* netlists: improve stats.Tristan Gingold2020-05-181-3/+73
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* netlits: Use Remove_Instance instead of Free_Instance.Tristan Gingold2020-05-185-44/+11
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* netlists: add disp_stats.Tristan Gingold2020-05-183-1/+42
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* netlists: add more flags in Module_Record.Tristan Gingold2020-05-182-15/+27
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* synth-expr: synth_subtype_conversion: add more assertions.Tristan Gingold2020-05-181-6/+7
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* synth-aggr: use constrainted type to build record aggregate.Tristan Gingold2020-05-181-1/+1
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* netlists-expands: remove memidx gates after expansion.Tristan Gingold2020-05-182-13/+29
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* vhdl-sem_psl: handle equal/goto repeat seq. Fix #1321Tristan Gingold2020-05-181-1/+3
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* synth-environment: fix handling of static values in case statements. Fix #1319Tristan Gingold2020-05-181-2/+2
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* netlists-inference: avoid a crash for assertions in case statement. Fix #1317Tristan Gingold2020-05-171-4/+9
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* synth-static_oper: detect integer overflow on arith operators. Fix #1316Tristan Gingold2020-05-171-13/+66
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* synth-ieee-std-logic_1164: remove unused std_logic_vector declaration.Tristan Gingold2020-05-171-4/+0
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* synth: move static comparison functions to synth.ieee.numericTristan Gingold2020-05-173-310/+304
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* synth: handle static shift in synth.ieee.numeric_std.Tristan Gingold2020-05-173-63/+78
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* synth-expr: handle array attribute on functions.Tristan Gingold2020-05-171-4/+7
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* synth-decls: can initialize a static variable with a constant.Tristan Gingold2020-05-161-0/+1
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* synth-ieee-numeric_std: also use memtyp for negation.Tristan Gingold2020-05-163-30/+20
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* synth: use memtyp for synth-ieee-numeric_std, add more signed mul.Tristan Gingold2020-05-165-486/+350
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* synth: use expanded name for assert labels. Fix #1314Tristan Gingold2020-05-161-8/+11
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* synth: handle static calls to signed numeric_std + -. Fix #1313Tristan Gingold2020-05-163-3/+119
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* synth: handle functional call to numeric_std binary operators. For #1313Tristan Gingold2020-05-162-25/+35
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* synth: handle inout ports with default values. For #1312Tristan Gingold2020-05-162-2/+7
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* synth-static_oper: handle eq_sgn_int comparision. For #1310Tristan Gingold2020-05-151-0/+56
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* trans-chap3: factorize code.Tristan Gingold2020-05-151-11/+1
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* synth: handle non-text file (add signatures).Tristan Gingold2020-05-156-10/+90
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* vhdl-utils: factorize Get_File_Signature.Tristan Gingold2020-05-154-134/+113
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* synth: handle initialized inout port. For #1312Tristan Gingold2020-05-155-39/+72
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* synth-flags: consider severity error as an error.Tristan Gingold2020-05-151-1/+1
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* synth-static_oper: handle more comparisons. Fix #1310Tristan Gingold2020-05-151-0/+41
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* synth: handle null array comparison. Fix #1311Tristan Gingold2020-05-153-11/+45
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* synth-stmts: ignore choices with L/H/W/X/Z/-/U values.Tristan Gingold2020-05-151-6/+86
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* synth-aggr: create constrained record type if needed.Tristan Gingold2020-05-142-8/+28
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* synth-stmts: factorize code for assertion errors, use a level.Tristan Gingold2020-05-142-33/+27
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* grt: move severity levels from errors to grt.severity.Tristan Gingold2020-05-146-8/+40
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* synth-values: tentatively try to fix warnings. For #1308Tristan Gingold2020-05-131-8/+12
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* synth-objtypes: tentatively try to fix warnings. For #1308Tristan Gingold2020-05-131-32/+48
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* vhdl-configuration: handle overrides of slv. Fix #1298Tristan Gingold2020-05-131-1/+15
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* trans-chap7: add a comment.Tristan Gingold2020-05-131-0/+3
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* synth-objtypes: use Address to avoid compiler warnings. For #1308.Tristan Gingold2020-05-131-23/+22
| | | | | Use intermediate type Address to convert between Memory_Ptr and scalar types, as Address has no alignment.
* synth: handle any constant as edge value. Fix #1302Tristan Gingold2020-05-131-27/+37
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* trans-chap5: handle record subtypes in port association.Tristan Gingold2020-05-131-13/+22
| | | | Part of #1300
* trans-chap7: Translate_Equality: also convert to base type for records.Tristan Gingold2020-05-133-26/+51
| | | | For #1300
* vhdl: translate_record_subtype: inherit from parent typeTristan Gingold2020-05-121-18/+24
| | | | (instead of base type). For #1300
* Adding some comments to the RTI processing. (#1304)Ben Reynwar2020-05-123-15/+73
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