aboutsummaryrefslogtreecommitdiffstats
path: root/src
Commit message (Collapse)AuthorAgeFilesLines
* synth: handle array attributes; handle integer subtypes in generics.Tristan Gingold2019-08-162-2/+91
| | | | Fix tgingold/ghdlsynth-beta#32
* add synthesis support for logic operators on numeric types (#893)Pepijn de Vos2019-08-154-4/+149
| | | | | | | | * add logic operators on unsigned * handle signed too * handle unary not
* synth: fix handling of assume/assert.Tristan Gingold2019-08-141-6/+65
|
* ghdlsynth: add command to get libghdl paths.Tristan Gingold2019-08-144-22/+97
|
* ghdldrv: move command_str_disp from ghdlvpi to ghdlmainTristan Gingold2019-08-143-38/+38
|
* ghdlsynth: declare init_for_ghdl_synth.Tristan Gingold2019-08-141-1/+4
|
* vhdl: handle PSL keywords as vhdl08 reserved words; switch to PSL scanner mode.Tristan Gingold2019-08-142-0/+12
|
* vhdl: add PSL keywords to vhdl08 reserved words.Tristan Gingold2019-08-1410-242/+257
|
* synth: also extract edge in PSL expressions.Tristan Gingold2019-08-133-18/+36
|
* synth: extract edge for PSL clocks.Tristan Gingold2019-08-131-27/+34
|
* vhdl-nodes_walk: handle iir_kind_psl_default_clock.Tristan Gingold2019-08-131-1/+2
|
* libghdlsynth: make it almost empty, as libghdl will be used instead.Tristan Gingold2019-08-131-8/+0
|
* Support for PSL assert and assume in synthesis (#892)Pepijn de Vos2019-08-131-4/+53
| | | | | | | | * initial support for PSL assert and assume * add support for true, false, and, or in psl synth * update testsuite with new psl things
* libghdl: also add synthesis part. For #884Tristan Gingold2019-08-136-52/+56
|
* synth: build_header was replaced by a Makefile target.Tristan Gingold2019-08-131-8/+0
|
* libghdl: preliminary work to also support synth.Tristan Gingold2019-08-132-4/+9
|
* vhdl: improve reprint of inertial association.Tristan Gingold2019-08-116-181/+206
|
* vhdl-sem: fix minor thinko for sem_insert_anonymous_signal.Tristan Gingold2019-08-111-1/+24
| | | | Fix #885
* vhdl: avoid crash on incorrect unit name.Tristan Gingold2019-08-102-6/+36
| | | | Fix #886
* vhdl: handle subtype indication (with range) in discrete_range.Tristan Gingold2019-08-107-63/+105
| | | | For #877
* synth: add comments.Tristan Gingold2019-08-091-1/+9
|
* vhdl: remove unused Get/Set_Choice_Order.Tristan Gingold2019-08-095-304/+247
|
* synth: fix crash when assignment target is an aggregate.Tristan Gingold2019-08-081-5/+7
| | | | For tgingold/ghdlsynth-beta#26
* vhdl: remove -Whides warnings for processes without a label.Tristan Gingold2019-08-081-0/+9
|
* synth: handle 1 bit integer in disp_vhdl, fix range in synth-expr.Tristan Gingold2019-08-082-4/+13
|
* vhdl: remove severity from cover, report and severity from assume.Tristan Gingold2019-08-0811-142/+160
|
* vhdl-nodes: gather PSL nodes, regenerate nodes_meta.Tristan Gingold2019-08-072-125/+91
|
* Add support for PSL assumptions, used in formal verification (#880)Pepijn de Vos2019-08-0730-141/+334
| | | | | | | | | | | | | | | | | | | | | | | | | | * vhdl: make the parser understand PSL assume * assume does not actually have report according to the spec. Just a property. * add SPL assume to semantic analysis * canonicalise PSL assume * add assume to annotations * add PSL assume to simulation code * statement -> directive * add assume to translation files * update ticked24 testcase * correctly parse assume * add assume testcase * refactor chunk of duplicated code
* vhdl: allow discrete subtype indication for discrete_range.Tristan Gingold2019-08-065-45/+53
| | | | For #877
* vhdl: for time resolution, do not consider unit name from textio body.Tristan Gingold2019-08-062-10/+38
| | | | For #881
* synth: improve support of vhdl08. Fix #882Tristan Gingold2019-08-052-5/+22
|
* synth: add asserts in synth-valuesTristan Gingold2019-08-051-0/+5
|
* synth: handle subtype conversions.Tristan Gingold2019-08-055-73/+154
|
* synth: handle signed conversions in disp_vhdl.Tristan Gingold2019-08-051-2/+6
|
* synth: preliminary support of integer literals.Tristan Gingold2019-08-022-18/+67
|
* synth: add a debug procedure.Tristan Gingold2019-08-022-0/+22
|
* synth: improve error message for multiple assignments.Tristan Gingold2019-08-021-4/+20
|
* synth: handle signed integer comparisons (#878)Pepijn de Vos2019-08-013-0/+43
| | | | | | | | | | * comparisons with integer literals * display signed comparison nicely * revert literal size changes * properly display signed values
* synth: handle partial assignments in a process (WIP).Tristan Gingold2019-08-011-18/+75
|
* synth: refactoring in inference/environment.Tristan Gingold2019-08-013-7/+13
|
* synth: refactor inference, add comment, strengthen check.Tristan Gingold2019-08-014-31/+62
|
* synth: refactoring in synth-inference.Tristan Gingold2019-07-311-129/+137
|
* synth: add location on monadic operators.Tristan Gingold2019-07-311-7/+10
|
* synth: regenerate ghdlsynth_gates.hTristan Gingold2019-07-311-3/+4
|
* synth: fix a crash in instantiation.Tristan Gingold2019-07-312-8/+9
|
* synth: slightly improve output for indexes.Tristan Gingold2019-07-301-3/+7
|
* synth: adjust output for dyn_insert, add dpram2 test.Tristan Gingold2019-07-301-2/+2
|
* synth: fixes for indexed names.Tristan Gingold2019-07-303-3/+13
|
* synth: rework indexed names.Tristan Gingold2019-07-304-101/+106
|
* synth: handle more conversions in disp_vhdlTristan Gingold2019-07-291-1/+44
|
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-31 06:24:10 +0000