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* synth: support sequential conditional signal assignment.Tristan Gingold2019-08-272-0/+3
| | | | Fix tgingold/ghdlsynth-beta#40
* synth: rework partial assignmentsTristan Gingold2019-08-2710-182/+608
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* netlists-disp_vhdl: do not used literals for prefixes.Tristan Gingold2019-08-271-12/+53
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* ignore restrict in simulation (#897)Pepijn de Vos2019-08-202-18/+17
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* synth: add support for constant exponentiation.Tristan Gingold2019-08-201-0/+10
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* synth: set name to assert/assume gates.Tristan Gingold2019-08-204-12/+44
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* netlist: fix minor pasto.Tristan Gingold2019-08-201-1/+1
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* initial support for reduce and/or (#900)Pepijn de Vos2019-08-205-6/+52
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* vhdl psl: fully scan PSL keywords in scanner.Tristan Gingold2019-08-207-67/+148
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* vhdl-prints: handle architecture in verification unit hierarchical name.Tristan Gingold2019-08-201-0/+7
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* vhdl: handle architecture in verification unit hierarchical name.Tristan Gingold2019-08-203-13/+53
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* vhdl-prints: handle verification units.Tristan Gingold2019-08-201-318/+354
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* vhdl: handle assume in verification units.Tristan Gingold2019-08-205-1/+11
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* synth: analyze input files.Tristan Gingold2019-08-201-1/+8
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* synth: set location on assume/assert gates.Tristan Gingold2019-08-203-8/+19
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* synth: handle verification units.Tristan Gingold2019-08-2013-246/+450
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* synth: handle array attribute "length" (#895)marph912019-08-191-0/+10
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* synth: fix tgingold/ghdlsynth#34 (association).Tristan Gingold2019-08-171-2/+1
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* vhdl: parse verification unit (WIP).Tristan Gingold2019-08-1715-363/+549
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* synth: handle integer values in subtype conversion.Tristan Gingold2019-08-161-0/+2
| | | | For tgingold/ghdlsynth-beta#33
* synth: handle integers for displaying vhdl ports.Tristan Gingold2019-08-161-0/+10
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* vhdl: declare verification units (WIP).Tristan Gingold2019-08-1612-280/+551
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* vhdl: recognize PSL units reserved words.Tristan Gingold2019-08-166-14/+29
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* synth: handle array attributes; handle integer subtypes in generics.Tristan Gingold2019-08-162-2/+91
| | | | Fix tgingold/ghdlsynth-beta#32
* add synthesis support for logic operators on numeric types (#893)Pepijn de Vos2019-08-154-4/+149
| | | | | | | | * add logic operators on unsigned * handle signed too * handle unary not
* synth: fix handling of assume/assert.Tristan Gingold2019-08-141-6/+65
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* ghdlsynth: add command to get libghdl paths.Tristan Gingold2019-08-144-22/+97
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* ghdldrv: move command_str_disp from ghdlvpi to ghdlmainTristan Gingold2019-08-143-38/+38
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* ghdlsynth: declare init_for_ghdl_synth.Tristan Gingold2019-08-141-1/+4
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* vhdl: handle PSL keywords as vhdl08 reserved words; switch to PSL scanner mode.Tristan Gingold2019-08-142-0/+12
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* vhdl: add PSL keywords to vhdl08 reserved words.Tristan Gingold2019-08-1410-242/+257
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* synth: also extract edge in PSL expressions.Tristan Gingold2019-08-133-18/+36
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* synth: extract edge for PSL clocks.Tristan Gingold2019-08-131-27/+34
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* vhdl-nodes_walk: handle iir_kind_psl_default_clock.Tristan Gingold2019-08-131-1/+2
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* libghdlsynth: make it almost empty, as libghdl will be used instead.Tristan Gingold2019-08-131-8/+0
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* Support for PSL assert and assume in synthesis (#892)Pepijn de Vos2019-08-131-4/+53
| | | | | | | | * initial support for PSL assert and assume * add support for true, false, and, or in psl synth * update testsuite with new psl things
* libghdl: also add synthesis part. For #884Tristan Gingold2019-08-136-52/+56
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* synth: build_header was replaced by a Makefile target.Tristan Gingold2019-08-131-8/+0
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* libghdl: preliminary work to also support synth.Tristan Gingold2019-08-132-4/+9
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* vhdl: improve reprint of inertial association.Tristan Gingold2019-08-116-181/+206
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* vhdl-sem: fix minor thinko for sem_insert_anonymous_signal.Tristan Gingold2019-08-111-1/+24
| | | | Fix #885
* vhdl: avoid crash on incorrect unit name.Tristan Gingold2019-08-102-6/+36
| | | | Fix #886
* vhdl: handle subtype indication (with range) in discrete_range.Tristan Gingold2019-08-107-63/+105
| | | | For #877
* synth: add comments.Tristan Gingold2019-08-091-1/+9
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* vhdl: remove unused Get/Set_Choice_Order.Tristan Gingold2019-08-095-304/+247
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* synth: fix crash when assignment target is an aggregate.Tristan Gingold2019-08-081-5/+7
| | | | For tgingold/ghdlsynth-beta#26
* vhdl: remove -Whides warnings for processes without a label.Tristan Gingold2019-08-081-0/+9
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* synth: handle 1 bit integer in disp_vhdl, fix range in synth-expr.Tristan Gingold2019-08-082-4/+13
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* vhdl: remove severity from cover, report and severity from assume.Tristan Gingold2019-08-0811-142/+160
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* vhdl-nodes: gather PSL nodes, regenerate nodes_meta.Tristan Gingold2019-08-072-125/+91
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