From 5738c8a722b3eec9713bce9b83a5283a2001582f Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Wed, 7 Aug 2019 06:23:54 +0200
Subject: Add reproducer for tgingold/ghdlsynth-beta#26

---
 testsuite/synth/issue26/int_test.vhdl | 20 ++++++++++++++++++++
 testsuite/synth/issue26/testsuite.sh  |  9 +++++++++
 2 files changed, 29 insertions(+)
 create mode 100644 testsuite/synth/issue26/int_test.vhdl
 create mode 100755 testsuite/synth/issue26/testsuite.sh

diff --git a/testsuite/synth/issue26/int_test.vhdl b/testsuite/synth/issue26/int_test.vhdl
new file mode 100644
index 000000000..afc8c4cdb
--- /dev/null
+++ b/testsuite/synth/issue26/int_test.vhdl
@@ -0,0 +1,20 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity int_test is
+  port (clk : in std_logic;
+        a, b : in integer range 0 to 1;
+        c : out std_logic);
+end int_test;
+
+architecture rtl of int_test is
+begin
+  process (clk)
+  begin
+    if rising_edge (clk) then
+      if a < b then
+        c <= '0';
+      end if;
+    end if;
+  end process;
+end rtl;
diff --git a/testsuite/synth/issue26/testsuite.sh b/testsuite/synth/issue26/testsuite.sh
new file mode 100755
index 000000000..1cc0536d7
--- /dev/null
+++ b/testsuite/synth/issue26/testsuite.sh
@@ -0,0 +1,9 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth int_test.vhdl -e int_test > syn_int_test.vhdl
+analyze syn_int_test.vhdl
+clean
+
+echo "Test successful"
-- 
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