From 5cfb8e78cd5d7bdc83494bd72cbe17bf4921bda8 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Wed, 14 Aug 2019 08:22:20 +0200 Subject: vhdl: add PSL keywords to vhdl08 reserved words. --- src/ghdldrv/ghdlprint.adb | 11 +- src/std_names.adb | 44 +++---- src/std_names.ads | 268 ++++++++++++++++++++++--------------------- src/vhdl/vhdl-formatters.adb | 2 +- src/vhdl/vhdl-parse.adb | 70 ++++++----- src/vhdl/vhdl-parse_psl.adb | 8 +- src/vhdl/vhdl-prints.adb | 12 +- src/vhdl/vhdl-scanner.adb | 42 +++++-- src/vhdl/vhdl-tokens.adb | 28 ++--- src/vhdl/vhdl-tokens.ads | 14 +-- 10 files changed, 257 insertions(+), 242 deletions(-) diff --git a/src/ghdldrv/ghdlprint.adb b/src/ghdldrv/ghdlprint.adb index a611f07e7..65eec4ed3 100644 --- a/src/ghdldrv/ghdlprint.adb +++ b/src/ghdldrv/ghdlprint.adb @@ -383,22 +383,15 @@ package body Ghdlprint is Disp_Text; Put (""); end case; - when Tok_Mod .. Tok_Parameter => + when Tok_Mod .. Tok_Sequence => Disp_Reserved; when Tok_Semi_Colon => Disp_Spaces; Disp_Text; when Tok_Across .. Tok_Tolerance => Disp_Reserved; - when Tok_Psl_Default - | Tok_Psl_Clock - | Tok_Psl_Property - | Tok_Psl_Sequence + when Tok_Psl_Clock | Tok_Psl_Endpoint - | Tok_Psl_Assume - | Tok_Psl_Cover - | Tok_Psl_Restrict - | Tok_Psl_Restrict_Guarantee | Tok_Psl_Boolean | Tok_Psl_Const | Tok_Inf diff --git a/src/std_names.adb b/src/std_names.adb index e06c814a1..e13c010e6 100644 --- a/src/std_names.adb +++ b/src/std_names.adb @@ -153,22 +153,29 @@ package body Std_Names is Def ("protected", Name_Protected); - Def ("context", Name_Context); - Def ("parameter", Name_Parameter); - - Def ("across", Name_Across); - Def ("break", Name_Break); - Def ("limit", Name_Limit); - Def ("nature", Name_Nature); - Def ("noise", Name_Noise); + Def ("assume", Name_Assume); + Def ("context", Name_Context); + Def ("cover", Name_Cover); + Def ("default", Name_Default); + Def ("parameter", Name_Parameter); + Def ("property", Name_Property); + Def ("restrict", Name_Restrict); + Def ("restrict_guarantee", Name_Restrict_Guarantee); + Def ("sequence", Name_Sequence); + + Def ("across", Name_Across); + Def ("break", Name_Break); + Def ("limit", Name_Limit); + Def ("nature", Name_Nature); + Def ("noise", Name_Noise); Def ("procedural", Name_Procedural); - Def ("quantity", Name_Quantity); - Def ("reference", Name_Reference); - Def ("spectrum", Name_Spectrum); - Def ("subnature", Name_Subnature); - Def ("terminal", Name_Terminal); - Def ("through", Name_Through); - Def ("tolerance", Name_Tolerance); + Def ("quantity", Name_Quantity); + Def ("reference", Name_Reference); + Def ("spectrum", Name_Spectrum); + Def ("subnature", Name_Subnature); + Def ("terminal", Name_Terminal); + Def ("through", Name_Through); + Def ("tolerance", Name_Tolerance); -- Verilog keywords Def ("always", Name_Always); @@ -180,7 +187,6 @@ package body Std_Names is Def ("casez", Name_Casez); Def ("cmos", Name_Cmos); Def ("deassign", Name_Deassign); - Def ("default", Name_Default); Def ("defparam", Name_Defparam); Def ("disable", Name_Disable); Def ("edge", Name_Edge); @@ -324,7 +330,6 @@ package body Std_Names is Def ("join_none", Name_Join_None); Def ("local", Name_Local); Def ("program", Name_Program); - Def ("property", Name_Property); Def ("rand", Name_Rand); Def ("randc", Name_Randc); Def ("ref", Name_Ref); @@ -339,7 +344,6 @@ package body Std_Names is Def ("wait_order", Name_Wait_Order); -- SystemVerilog 3.1a - Def ("assume", Name_Assume); Def ("covergroup", Name_Covergroup); Def ("coverpoint", Name_Coverpoint); Def ("endgroup", Name_Endgroup); @@ -759,7 +763,6 @@ package body Std_Names is Def ("before", Name_Before); Def ("clock", Name_Clock); Def ("const", Name_Const); - Def ("cover", Name_Cover); Def ("e", Name_E); Def ("ef", Name_Ef); Def ("eg", Name_Eg); @@ -780,10 +783,7 @@ package body Std_Names is Def ("next_event_e", Name_Next_Event_E); Def ("property", Name_Property); Def ("prev", Name_Prev); - Def ("restrict", Name_Restrict); - Def ("restrict_guarantee", Name_Restrict_Guarantee); Def ("rose", Name_Rose); - Def ("sequence", Name_Sequence); Def ("strong", Name_Strong); Def ("union", Name_Union); Def ("vmode", Name_Vmode); diff --git a/src/std_names.ads b/src/std_names.ads index 5d2e58e7f..0e08cac9d 100644 --- a/src/std_names.ads +++ b/src/std_names.ads @@ -172,14 +172,21 @@ package Std_Names is subtype Name_Id_Vhdl00_Reserved_Words is Name_Id range Name_Protected .. Name_Last_Vhdl00; - Name_Context : constant Name_Id := Name_First_Keyword + 098; - Name_Parameter : constant Name_Id := Name_First_Keyword + 099; - - Name_Last_Vhdl08 : constant Name_Id := Name_Parameter; + Name_Assume : constant Name_Id := Name_First_Keyword + 098; + Name_Context : constant Name_Id := Name_First_Keyword + 099; + Name_Cover : constant Name_Id := Name_First_Keyword + 100; + Name_Default : constant Name_Id := Name_First_Keyword + 101; + Name_Parameter : constant Name_Id := Name_First_Keyword + 102; + Name_Property : constant Name_Id := Name_First_Keyword + 103; + Name_Restrict : constant Name_Id := Name_First_Keyword + 104; + Name_Restrict_Guarantee : constant Name_Id := Name_First_Keyword + 105; + Name_Sequence : constant Name_Id := Name_First_Keyword + 106; + + Name_Last_Vhdl08 : constant Name_Id := Name_Sequence; subtype Name_Id_Vhdl08_Reserved_Words is - Name_Id range Name_Context .. Name_Last_Vhdl08; + Name_Id range Name_Assume .. Name_Last_Vhdl08; - Name_First_Ams_Keyword : constant Name_Id := Name_Last_Vhdl08 + 1; + Name_First_Ams_Keyword : constant Name_Id := Name_Last_Vhdl08 + 1; Name_Across : constant Name_Id := Name_First_Ams_Keyword + 000; Name_Break : constant Name_Id := Name_First_Ams_Keyword + 001; Name_Limit : constant Name_Id := Name_First_Ams_Keyword + 002; @@ -214,77 +221,76 @@ package Std_Names is Name_Casez : constant Name_Id := Name_First_Verilog + 06; Name_Cmos : constant Name_Id := Name_First_Verilog + 07; Name_Deassign : constant Name_Id := Name_First_Verilog + 08; - Name_Default : constant Name_Id := Name_First_Verilog + 09; - Name_Defparam : constant Name_Id := Name_First_Verilog + 10; - Name_Disable : constant Name_Id := Name_First_Verilog + 11; - Name_Edge : constant Name_Id := Name_First_Verilog + 12; - Name_Endcase : constant Name_Id := Name_First_Verilog + 13; - Name_Endfunction : constant Name_Id := Name_First_Verilog + 14; - Name_Endmodule : constant Name_Id := Name_First_Verilog + 15; - Name_Endprimitive : constant Name_Id := Name_First_Verilog + 16; - Name_Endspecify : constant Name_Id := Name_First_Verilog + 17; - Name_Endtable : constant Name_Id := Name_First_Verilog + 18; - Name_Endtask : constant Name_Id := Name_First_Verilog + 19; - Name_Force : constant Name_Id := Name_First_Verilog + 20; - Name_Forever : constant Name_Id := Name_First_Verilog + 21; - Name_Fork : constant Name_Id := Name_First_Verilog + 22; - Name_Highz0 : constant Name_Id := Name_First_Verilog + 23; - Name_Highz1 : constant Name_Id := Name_First_Verilog + 24; - Name_Ifnone : constant Name_Id := Name_First_Verilog + 25; - Name_Initial : constant Name_Id := Name_First_Verilog + 26; - Name_Input : constant Name_Id := Name_First_Verilog + 27; - Name_Join : constant Name_Id := Name_First_Verilog + 28; - Name_Large : constant Name_Id := Name_First_Verilog + 29; - Name_Macromodule : constant Name_Id := Name_First_Verilog + 30; - Name_Medium : constant Name_Id := Name_First_Verilog + 31; - Name_Module : constant Name_Id := Name_First_Verilog + 32; - Name_Negedge : constant Name_Id := Name_First_Verilog + 33; - Name_Nmos : constant Name_Id := Name_First_Verilog + 34; - Name_Notif0 : constant Name_Id := Name_First_Verilog + 35; - Name_Notif1 : constant Name_Id := Name_First_Verilog + 36; - Name_Output : constant Name_Id := Name_First_Verilog + 37; - Name_Pmos : constant Name_Id := Name_First_Verilog + 38; - Name_Posedge : constant Name_Id := Name_First_Verilog + 39; - Name_Primitive : constant Name_Id := Name_First_Verilog + 40; - Name_Pull0 : constant Name_Id := Name_First_Verilog + 41; - Name_Pull1 : constant Name_Id := Name_First_Verilog + 42; - Name_Pulldown : constant Name_Id := Name_First_Verilog + 43; - Name_Pullup : constant Name_Id := Name_First_Verilog + 44; - Name_Realtime : constant Name_Id := Name_First_Verilog + 45; - Name_Release : constant Name_Id := Name_First_Verilog + 46; - Name_Reg : constant Name_Id := Name_First_Verilog + 47; - Name_Repeat : constant Name_Id := Name_First_Verilog + 48; - Name_Rcmos : constant Name_Id := Name_First_Verilog + 49; - Name_Rnmos : constant Name_Id := Name_First_Verilog + 50; - Name_Rpmos : constant Name_Id := Name_First_Verilog + 51; - Name_Rtran : constant Name_Id := Name_First_Verilog + 52; - Name_Rtranif0 : constant Name_Id := Name_First_Verilog + 53; - Name_Rtranif1 : constant Name_Id := Name_First_Verilog + 54; - Name_Scalared : constant Name_Id := Name_First_Verilog + 55; - Name_Small : constant Name_Id := Name_First_Verilog + 56; - Name_Specify : constant Name_Id := Name_First_Verilog + 57; - Name_Specparam : constant Name_Id := Name_First_Verilog + 58; - Name_Strong0 : constant Name_Id := Name_First_Verilog + 59; - Name_Strong1 : constant Name_Id := Name_First_Verilog + 60; - Name_Supply0 : constant Name_Id := Name_First_Verilog + 61; - Name_Supply1 : constant Name_Id := Name_First_Verilog + 62; - Name_Tablex : constant Name_Id := Name_First_Verilog + 63; - Name_Task : constant Name_Id := Name_First_Verilog + 64; - Name_Tran : constant Name_Id := Name_First_Verilog + 65; - Name_Tranif0 : constant Name_Id := Name_First_Verilog + 66; - Name_Tranif1 : constant Name_Id := Name_First_Verilog + 67; - Name_Tri : constant Name_Id := Name_First_Verilog + 68; - Name_Tri0 : constant Name_Id := Name_First_Verilog + 69; - Name_Tri1 : constant Name_Id := Name_First_Verilog + 70; - Name_Triand : constant Name_Id := Name_First_Verilog + 71; - Name_Trior : constant Name_Id := Name_First_Verilog + 72; - Name_Trireg : constant Name_Id := Name_First_Verilog + 73; - Name_Vectored : constant Name_Id := Name_First_Verilog + 74; - Name_Wand : constant Name_Id := Name_First_Verilog + 75; - Name_Weak0 : constant Name_Id := Name_First_Verilog + 76; - Name_Weak1 : constant Name_Id := Name_First_Verilog + 77; - Name_Wire : constant Name_Id := Name_First_Verilog + 78; - Name_Wor : constant Name_Id := Name_First_Verilog + 79; + Name_Defparam : constant Name_Id := Name_First_Verilog + 09; + Name_Disable : constant Name_Id := Name_First_Verilog + 10; + Name_Edge : constant Name_Id := Name_First_Verilog + 11; + Name_Endcase : constant Name_Id := Name_First_Verilog + 12; + Name_Endfunction : constant Name_Id := Name_First_Verilog + 13; + Name_Endmodule : constant Name_Id := Name_First_Verilog + 14; + Name_Endprimitive : constant Name_Id := Name_First_Verilog + 15; + Name_Endspecify : constant Name_Id := Name_First_Verilog + 16; + Name_Endtable : constant Name_Id := Name_First_Verilog + 17; + Name_Endtask : constant Name_Id := Name_First_Verilog + 18; + Name_Force : constant Name_Id := Name_First_Verilog + 19; + Name_Forever : constant Name_Id := Name_First_Verilog + 20; + Name_Fork : constant Name_Id := Name_First_Verilog + 21; + Name_Highz0 : constant Name_Id := Name_First_Verilog + 22; + Name_Highz1 : constant Name_Id := Name_First_Verilog + 23; + Name_Ifnone : constant Name_Id := Name_First_Verilog + 24; + Name_Initial : constant Name_Id := Name_First_Verilog + 25; + Name_Input : constant Name_Id := Name_First_Verilog + 26; + Name_Join : constant Name_Id := Name_First_Verilog + 27; + Name_Large : constant Name_Id := Name_First_Verilog + 28; + Name_Macromodule : constant Name_Id := Name_First_Verilog + 29; + Name_Medium : constant Name_Id := Name_First_Verilog + 30; + Name_Module : constant Name_Id := Name_First_Verilog + 31; + Name_Negedge : constant Name_Id := Name_First_Verilog + 32; + Name_Nmos : constant Name_Id := Name_First_Verilog + 33; + Name_Notif0 : constant Name_Id := Name_First_Verilog + 34; + Name_Notif1 : constant Name_Id := Name_First_Verilog + 35; + Name_Output : constant Name_Id := Name_First_Verilog + 36; + Name_Pmos : constant Name_Id := Name_First_Verilog + 37; + Name_Posedge : constant Name_Id := Name_First_Verilog + 38; + Name_Primitive : constant Name_Id := Name_First_Verilog + 39; + Name_Pull0 : constant Name_Id := Name_First_Verilog + 40; + Name_Pull1 : constant Name_Id := Name_First_Verilog + 41; + Name_Pulldown : constant Name_Id := Name_First_Verilog + 42; + Name_Pullup : constant Name_Id := Name_First_Verilog + 43; + Name_Realtime : constant Name_Id := Name_First_Verilog + 44; + Name_Release : constant Name_Id := Name_First_Verilog + 45; + Name_Reg : constant Name_Id := Name_First_Verilog + 46; + Name_Repeat : constant Name_Id := Name_First_Verilog + 47; + Name_Rcmos : constant Name_Id := Name_First_Verilog + 48; + Name_Rnmos : constant Name_Id := Name_First_Verilog + 49; + Name_Rpmos : constant Name_Id := Name_First_Verilog + 50; + Name_Rtran : constant Name_Id := Name_First_Verilog + 51; + Name_Rtranif0 : constant Name_Id := Name_First_Verilog + 52; + Name_Rtranif1 : constant Name_Id := Name_First_Verilog + 53; + Name_Scalared : constant Name_Id := Name_First_Verilog + 54; + Name_Small : constant Name_Id := Name_First_Verilog + 55; + Name_Specify : constant Name_Id := Name_First_Verilog + 56; + Name_Specparam : constant Name_Id := Name_First_Verilog + 57; + Name_Strong0 : constant Name_Id := Name_First_Verilog + 58; + Name_Strong1 : constant Name_Id := Name_First_Verilog + 59; + Name_Supply0 : constant Name_Id := Name_First_Verilog + 60; + Name_Supply1 : constant Name_Id := Name_First_Verilog + 61; + Name_Tablex : constant Name_Id := Name_First_Verilog + 62; + Name_Task : constant Name_Id := Name_First_Verilog + 63; + Name_Tran : constant Name_Id := Name_First_Verilog + 64; + Name_Tranif0 : constant Name_Id := Name_First_Verilog + 65; + Name_Tranif1 : constant Name_Id := Name_First_Verilog + 66; + Name_Tri : constant Name_Id := Name_First_Verilog + 67; + Name_Tri0 : constant Name_Id := Name_First_Verilog + 68; + Name_Tri1 : constant Name_Id := Name_First_Verilog + 69; + Name_Triand : constant Name_Id := Name_First_Verilog + 70; + Name_Trior : constant Name_Id := Name_First_Verilog + 71; + Name_Trireg : constant Name_Id := Name_First_Verilog + 72; + Name_Vectored : constant Name_Id := Name_First_Verilog + 73; + Name_Wand : constant Name_Id := Name_First_Verilog + 74; + Name_Weak0 : constant Name_Id := Name_First_Verilog + 75; + Name_Weak1 : constant Name_Id := Name_First_Verilog + 76; + Name_Wire : constant Name_Id := Name_First_Verilog + 77; + Name_Wor : constant Name_Id := Name_First_Verilog + 78; Name_Last_Verilog : constant Name_Id := Name_Wor; -- Verilog 2001 @@ -347,53 +353,49 @@ package Std_Names is Name_Class : constant Name_Id := Name_First_SV3_1 + 1; Name_Clocking : constant Name_Id := Name_First_SV3_1 + 2; Name_Constraint : constant Name_Id := Name_First_SV3_1 + 3; - Name_Cover : constant Name_Id := Name_First_SV3_1 + 4; - Name_Dist : constant Name_Id := Name_First_SV3_1 + 5; - Name_Endclass : constant Name_Id := Name_First_SV3_1 + 6; - Name_Endclocking : constant Name_Id := Name_First_SV3_1 + 7; - Name_Endprogram : constant Name_Id := Name_First_SV3_1 + 8; - Name_Endproperty : constant Name_Id := Name_First_SV3_1 + 9; - Name_Endsequence : constant Name_Id := Name_First_SV3_1 + 10; - Name_Extends : constant Name_Id := Name_First_SV3_1 + 11; - Name_Final : constant Name_Id := Name_First_SV3_1 + 12; - Name_First_Match : constant Name_Id := Name_First_SV3_1 + 13; - Name_Inside : constant Name_Id := Name_First_SV3_1 + 14; - Name_Intersect : constant Name_Id := Name_First_SV3_1 + 15; - Name_Join_Any : constant Name_Id := Name_First_SV3_1 + 16; - Name_Join_None : constant Name_Id := Name_First_SV3_1 + 17; - Name_Local : constant Name_Id := Name_First_SV3_1 + 18; - Name_Program : constant Name_Id := Name_First_SV3_1 + 19; - Name_Property : constant Name_Id := Name_First_SV3_1 + 20; - Name_Rand : constant Name_Id := Name_First_SV3_1 + 21; - Name_Randc : constant Name_Id := Name_First_SV3_1 + 22; - Name_Ref : constant Name_Id := Name_First_SV3_1 + 23; - Name_Sequence : constant Name_Id := Name_First_SV3_1 + 24; - Name_Solve : constant Name_Id := Name_First_SV3_1 + 25; - Name_String : constant Name_Id := Name_First_SV3_1 + 26; - Name_Super : constant Name_Id := Name_First_SV3_1 + 27; - Name_This : constant Name_Id := Name_First_SV3_1 + 28; - Name_Throughout : constant Name_Id := Name_First_SV3_1 + 29; - Name_Var : constant Name_Id := Name_First_SV3_1 + 30; - Name_Virtual : constant Name_Id := Name_First_SV3_1 + 31; - Name_Wait_Order : constant Name_Id := Name_First_SV3_1 + 32; + Name_Dist : constant Name_Id := Name_First_SV3_1 + 4; + Name_Endclass : constant Name_Id := Name_First_SV3_1 + 5; + Name_Endclocking : constant Name_Id := Name_First_SV3_1 + 6; + Name_Endprogram : constant Name_Id := Name_First_SV3_1 + 7; + Name_Endproperty : constant Name_Id := Name_First_SV3_1 + 8; + Name_Endsequence : constant Name_Id := Name_First_SV3_1 + 9; + Name_Extends : constant Name_Id := Name_First_SV3_1 + 10; + Name_Final : constant Name_Id := Name_First_SV3_1 + 11; + Name_First_Match : constant Name_Id := Name_First_SV3_1 + 12; + Name_Inside : constant Name_Id := Name_First_SV3_1 + 13; + Name_Intersect : constant Name_Id := Name_First_SV3_1 + 14; + Name_Join_Any : constant Name_Id := Name_First_SV3_1 + 15; + Name_Join_None : constant Name_Id := Name_First_SV3_1 + 16; + Name_Local : constant Name_Id := Name_First_SV3_1 + 17; + Name_Program : constant Name_Id := Name_First_SV3_1 + 18; + Name_Rand : constant Name_Id := Name_First_SV3_1 + 19; + Name_Randc : constant Name_Id := Name_First_SV3_1 + 20; + Name_Ref : constant Name_Id := Name_First_SV3_1 + 21; + Name_Solve : constant Name_Id := Name_First_SV3_1 + 22; + Name_String : constant Name_Id := Name_First_SV3_1 + 23; + Name_Super : constant Name_Id := Name_First_SV3_1 + 24; + Name_This : constant Name_Id := Name_First_SV3_1 + 25; + Name_Throughout : constant Name_Id := Name_First_SV3_1 + 26; + Name_Var : constant Name_Id := Name_First_SV3_1 + 27; + Name_Virtual : constant Name_Id := Name_First_SV3_1 + 28; + Name_Wait_Order : constant Name_Id := Name_First_SV3_1 + 29; Name_Last_SV3_1 : constant Name_Id := Name_Wait_Order; Name_First_SV3_1a : constant Name_Id := Name_Last_SV3_1 + 1; - Name_Assume : constant Name_Id := Name_First_SV3_1a + 0; - Name_Covergroup : constant Name_Id := Name_First_SV3_1a + 1; - Name_Coverpoint : constant Name_Id := Name_First_SV3_1a + 2; - Name_Endgroup : constant Name_Id := Name_First_SV3_1a + 3; - Name_Endpackage : constant Name_Id := Name_First_SV3_1a + 4; - Name_Expect : constant Name_Id := Name_First_SV3_1a + 5; - Name_Foreach : constant Name_Id := Name_First_SV3_1a + 6; - Name_Ignore_Bins : constant Name_Id := Name_First_SV3_1a + 7; - Name_Illegal_Bins : constant Name_Id := Name_First_SV3_1a + 8; - Name_Matches : constant Name_Id := Name_First_SV3_1a + 9; - Name_Randcase : constant Name_Id := Name_First_SV3_1a + 10; - Name_Randsequence : constant Name_Id := Name_First_SV3_1a + 11; - Name_Tagged : constant Name_Id := Name_First_SV3_1a + 12; - Name_Wildcard : constant Name_Id := Name_First_SV3_1a + 13; - Name_Last_SV3_1a : constant Name_Id := Name_First_SV3_1a + 13; + Name_Covergroup : constant Name_Id := Name_First_SV3_1a + 0; + Name_Coverpoint : constant Name_Id := Name_First_SV3_1a + 1; + Name_Endgroup : constant Name_Id := Name_First_SV3_1a + 2; + Name_Endpackage : constant Name_Id := Name_First_SV3_1a + 3; + Name_Expect : constant Name_Id := Name_First_SV3_1a + 4; + Name_Foreach : constant Name_Id := Name_First_SV3_1a + 5; + Name_Ignore_Bins : constant Name_Id := Name_First_SV3_1a + 6; + Name_Illegal_Bins : constant Name_Id := Name_First_SV3_1a + 7; + Name_Matches : constant Name_Id := Name_First_SV3_1a + 8; + Name_Randcase : constant Name_Id := Name_First_SV3_1a + 9; + Name_Randsequence : constant Name_Id := Name_First_SV3_1a + 10; + Name_Tagged : constant Name_Id := Name_First_SV3_1a + 11; + Name_Wildcard : constant Name_Id := Name_First_SV3_1a + 12; + Name_Last_SV3_1a : constant Name_Id := Name_Wildcard; Name_First_SV2009 : constant Name_Id := Name_Last_SV3_1a + 1; Name_Implies : constant Name_Id := Name_First_SV2009 + 0; @@ -918,21 +920,21 @@ package Std_Names is -- Name_Or -- Name_Property Name_Prev : constant Name_Id := Name_First_PSL + 26; - Name_Restrict : constant Name_Id := Name_First_PSL + 27; - Name_Restrict_Guarantee : constant Name_Id := Name_First_PSL + 28; - Name_Rose : constant Name_Id := Name_First_PSL + 29; + -- Name_Restrict + -- Name_Restrict_Guarantee + Name_Rose : constant Name_Id := Name_First_PSL + 27; -- sequence - Name_Strong : constant Name_Id := Name_First_PSL + 30; + Name_Strong : constant Name_Id := Name_First_PSL + 28; -- union -- until - Name_Vmode : constant Name_Id := Name_First_PSL + 31; - Name_Vprop : constant Name_Id := Name_First_PSL + 32; - Name_Vunit : constant Name_Id := Name_First_PSL + 33; - Name_W : constant Name_Id := Name_First_PSL + 34; - Name_Whilenot : constant Name_Id := Name_First_PSL + 35; - Name_Within : constant Name_Id := Name_First_PSL + 36; - Name_X : constant Name_Id := Name_First_PSL + 37; - Name_Last_PSL : constant Name_Id := Name_First_PSL + 37; + Name_Vmode : constant Name_Id := Name_First_PSL + 29; + Name_Vprop : constant Name_Id := Name_First_PSL + 30; + Name_Vunit : constant Name_Id := Name_First_PSL + 31; + Name_W : constant Name_Id := Name_First_PSL + 32; + Name_Whilenot : constant Name_Id := Name_First_PSL + 33; + Name_Within : constant Name_Id := Name_First_PSL + 34; + Name_X : constant Name_Id := Name_First_PSL + 35; + Name_Last_PSL : constant Name_Id := Name_X; subtype Name_Id_PSL_Keywords is Name_Id range Name_First_PSL .. Name_Last_PSL; diff --git a/src/vhdl/vhdl-formatters.adb b/src/vhdl/vhdl-formatters.adb index f6103f571..807436033 100644 --- a/src/vhdl/vhdl-formatters.adb +++ b/src/vhdl/vhdl-formatters.adb @@ -36,7 +36,7 @@ package body Vhdl.Formatters is or else Current_Token = Tok_Subtype) then null; - elsif (Tok = Tok_Psl_Default + elsif (Tok = Tok_Default or else Tok = Tok_Psl_Clock) and then Current_Token = Tok_Identifier then diff --git a/src/vhdl/vhdl-parse.adb b/src/vhdl/vhdl-parse.adb index 8800da259..e10786022 100644 --- a/src/vhdl/vhdl-parse.adb +++ b/src/vhdl/vhdl-parse.adb @@ -4981,38 +4981,34 @@ package body Vhdl.Parse is -- Skip ';'. Scan; end if; - when Tok_Identifier => - if Vhdl_Std >= Vhdl_08 - and then Current_Identifier = Name_Default - then - -- This identifier is a PSL keyword. - Xrefs.Xref_Keyword (Get_Token_Location); + when Tok_Default => + -- This identifier is a PSL keyword. + Xrefs.Xref_Keyword (Get_Token_Location); - -- Check whether default clock are allowed in this region. - case Get_Kind (Parent) is - when Iir_Kind_Function_Body - | Iir_Kind_Procedure_Body - | Iir_Kinds_Process_Statement - | Iir_Kind_Protected_Type_Body - | Iir_Kind_Package_Declaration - | Iir_Kind_Package_Body - | Iir_Kind_Protected_Type_Declaration => - Error_Msg_Parse - ("PSL default clock declaration not allowed here"); - when Iir_Kind_Entity_Declaration - | Iir_Kind_Architecture_Body - | Iir_Kind_Block_Statement - | Iir_Kind_Generate_Statement_Body => - null; - when others => - Error_Kind ("parse_declarative_part", Parent); - end case; - Decl := Parse_Psl_Default_Clock; - else - Error_Msg_Parse - ("object class keyword such as 'variable' is expected"); - Resync_To_End_Of_Declaration; - end if; + -- Check whether default clock are allowed in this region. + case Get_Kind (Parent) is + when Iir_Kind_Function_Body + | Iir_Kind_Procedure_Body + | Iir_Kinds_Process_Statement + | Iir_Kind_Protected_Type_Body + | Iir_Kind_Package_Declaration + | Iir_Kind_Package_Body + | Iir_Kind_Protected_Type_Declaration => + Error_Msg_Parse + ("PSL default clock declaration not allowed here"); + when Iir_Kind_Entity_Declaration + | Iir_Kind_Architecture_Body + | Iir_Kind_Block_Statement + | Iir_Kind_Generate_Statement_Body => + null; + when others => + Error_Kind ("parse_declarative_part", Parent); + end case; + Decl := Parse_Psl_Default_Clock; + when Tok_Identifier => + Error_Msg_Parse + ("object class keyword such as 'variable' is expected"); + Resync_To_End_Of_Declaration; when Tok_Semi_Colon => Error_Msg_Parse ("';' (semi colon) not allowed alone"); Scan; @@ -8836,23 +8832,23 @@ package body Vhdl.Parse is Stmt := Parse_Component_Instantiation (Unit); Set_Has_Component (Stmt, Has_Component); end; - when Tok_Psl_Default => + when Tok_Default => Postponed_Not_Allowed; Label_Not_Allowed; Stmt := Parse_Psl_Default_Clock; - when Tok_Psl_Property - | Tok_Psl_Sequence + when Tok_Property + | Tok_Sequence | Tok_Psl_Endpoint => Postponed_Not_Allowed; Label_Not_Allowed; Stmt := Parse_Psl_Declaration; - when Tok_Psl_Assume => + when Tok_Assume => Postponed_Not_Allowed; Stmt := Parse_Psl_Assume_Directive; - when Tok_Psl_Cover => + when Tok_Cover => Postponed_Not_Allowed; Stmt := Parse_Psl_Cover_Directive; - when Tok_Psl_Restrict => + when Tok_Restrict => Postponed_Not_Allowed; Stmt := Parse_Psl_Restrict_Directive; when Tok_Wait diff --git a/src/vhdl/vhdl-parse_psl.adb b/src/vhdl/vhdl-parse_psl.adb index 561f9caff..b4957b1ab 100644 --- a/src/vhdl/vhdl-parse_psl.adb +++ b/src/vhdl/vhdl-parse_psl.adb @@ -812,9 +812,9 @@ package body Vhdl.Parse_Psl is Kind : Nkind; begin case Tok is - when Tok_Psl_Property => + when Tok_Property => Kind := N_Property_Declaration; - when Tok_Psl_Sequence => + when Tok_Sequence => Kind := N_Sequence_Declaration; when Tok_Psl_Endpoint => Kind := N_Endpoint_Declaration; @@ -838,9 +838,9 @@ package body Vhdl.Parse_Psl is Pkind := N_Const_Parameter; when Tok_Psl_Boolean => Pkind := N_Boolean_Parameter; - when Tok_Psl_Property => + when Tok_Property => Pkind := N_Property_Parameter; - when Tok_Psl_Sequence => + when Tok_Sequence => Pkind := N_Sequence_Parameter; when others => Error_Msg_Parse ("parameter type expected"); diff --git a/src/vhdl/vhdl-prints.adb b/src/vhdl/vhdl-prints.adb index b66bb57ed..09c6f5ff4 100644 --- a/src/vhdl/vhdl-prints.adb +++ b/src/vhdl/vhdl-prints.adb @@ -2116,7 +2116,7 @@ package body Vhdl.Prints is if Vhdl_Std < Vhdl_08 then OOB.Put ("--psl "); end if; - Disp_Token (Ctxt, Tok_Psl_Default, Tok_Psl_Clock); + Disp_Token (Ctxt, Tok_Default, Tok_Psl_Clock); Disp_Token (Ctxt, Tok_Is); Disp_Psl_Expression (Ctxt, Get_Psl_Boolean (Stmt)); Disp_Token (Ctxt, Tok_Semi_Colon); @@ -2132,13 +2132,13 @@ package body Vhdl.Prints is end if; case Get_Kind (Decl) is when N_Property_Declaration => - Disp_Token (Ctxt, Tok_Psl_Property); + Disp_Token (Ctxt, Tok_Property); Disp_Ident (Ctxt, Get_Identifier (Decl)); Disp_Token (Ctxt, Tok_Is); Disp_Psl_Expression (Ctxt, Get_Property (Decl)); Disp_Token (Ctxt, Tok_Semi_Colon); when N_Sequence_Declaration => - Disp_Token (Ctxt, Tok_Psl_Sequence); + Disp_Token (Ctxt, Tok_Sequence); Disp_Ident (Ctxt, Get_Identifier (Decl)); Disp_Token (Ctxt, Tok_Is); Print_Sequence (Ctxt, Get_Sequence (Decl)); @@ -3926,7 +3926,7 @@ package body Vhdl.Prints is end if; Disp_Label (Ctxt, Stmt); Disp_Postponed (Ctxt, Stmt); - Disp_Token (Ctxt, Tok_Psl_Assume); + Disp_Token (Ctxt, Tok_Assume); Disp_Psl_Expression (Ctxt, Get_Psl_Property (Stmt)); Disp_Token (Ctxt, Tok_Semi_Colon); Close_Hbox (Ctxt); @@ -3941,7 +3941,7 @@ package body Vhdl.Prints is OOB.Put ("--psl "); end if; Disp_Label (Ctxt, Stmt); - Disp_Token (Ctxt, Tok_Psl_Cover); + Disp_Token (Ctxt, Tok_Cover); Print_Sequence (Ctxt, Get_Psl_Sequence (Stmt)); Disp_Report_Expression (Ctxt, Stmt); Disp_Token (Ctxt, Tok_Semi_Colon); @@ -3957,7 +3957,7 @@ package body Vhdl.Prints is OOB.Put ("--psl "); end if; Disp_Label (Ctxt, Stmt); - Disp_Token (Ctxt, Tok_Psl_Restrict); + Disp_Token (Ctxt, Tok_Restrict); Print_Sequence (Ctxt, Get_Psl_Sequence (Stmt)); Disp_Token (Ctxt, Tok_Semi_Colon); Close_Hbox (Ctxt); diff --git a/src/vhdl/vhdl-scanner.adb b/src/vhdl/vhdl-scanner.adb index 2f08ffbab..e71b2936e 100644 --- a/src/vhdl/vhdl-scanner.adb +++ b/src/vhdl/vhdl-scanner.adb @@ -1255,13 +1255,37 @@ package body Vhdl.Scanner is end if; when Std_Names.Name_Id_Vhdl08_Reserved_Words => if Vhdl_Std < Vhdl_08 then - if Is_Warning_Enabled (Warnid_Reserved_Word) then + -- Some vhdl08 reserved words are PSL keywords. + if Flag_Psl then + case Current_Identifier is + when Std_Names.Name_Sequence => + Current_Token := Tok_Sequence; + when Std_Names.Name_Property => + Current_Token := Tok_Property; + when Std_Names.Name_Assume => + Current_Token := Tok_Assume; + when Std_Names.Name_Cover => + Current_Token := Tok_Cover; + when Std_Names.Name_Default => + Current_Token := Tok_Default; + when Std_Names.Name_Restrict => + Current_Token := Tok_Restrict; + when Std_Names.Name_Restrict_Guarantee => + Current_Token := Tok_Restrict_Guarantee; + when others => + Current_Token := Tok_Identifier; + end case; + else + Current_Token := Tok_Identifier; + end if; + if Is_Warning_Enabled (Warnid_Reserved_Word) + and then Current_Token = Tok_Identifier + then Warning_Msg_Scan (Warnid_Reserved_Word, "using %i vhdl-2008 reserved word as an identifier", +Current_Identifier); end if; - Current_Token := Tok_Identifier; end if; when Std_Names.Name_Id_Vhdl00_Reserved_Words => if Vhdl_Std < Vhdl_00 then @@ -1302,21 +1326,21 @@ package body Vhdl.Scanner is when Std_Names.Name_Boolean => Current_Token := Tok_Psl_Boolean; when Std_Names.Name_Sequence => - Current_Token := Tok_Psl_Sequence; + Current_Token := Tok_Sequence; when Std_Names.Name_Property => - Current_Token := Tok_Psl_Property; + Current_Token := Tok_Property; when Std_Names.Name_Endpoint => Current_Token := Tok_Psl_Endpoint; when Std_Names.Name_Assume => - Current_Token := Tok_Psl_Assume; + Current_Token := Tok_Assume; when Std_Names.Name_Cover => - Current_Token := Tok_Psl_Cover; + Current_Token := Tok_Cover; when Std_Names.Name_Default => - Current_Token := Tok_Psl_Default; + Current_Token := Tok_Default; when Std_Names.Name_Restrict => - Current_Token := Tok_Psl_Restrict; + Current_Token := Tok_Restrict; when Std_Names.Name_Restrict_Guarantee => - Current_Token := Tok_Psl_Restrict_Guarantee; + Current_Token := Tok_Restrict_Guarantee; when Std_Names.Name_Inf => Current_Token := Tok_Inf; when Std_Names.Name_Within => diff --git a/src/vhdl/vhdl-tokens.adb b/src/vhdl/vhdl-tokens.adb index 1f17c5092..b06f916d7 100644 --- a/src/vhdl/vhdl-tokens.adb +++ b/src/vhdl/vhdl-tokens.adb @@ -352,10 +352,24 @@ package body Vhdl.Tokens is return "protected"; -- VHDL 08 + when Tok_Assume => + return "assume"; when Tok_Context => return "context"; + when Tok_Cover => + return "cover"; + when Tok_Default => + return "default"; when Tok_Parameter => return "parameter"; + when Tok_Property => + return "property"; + when Tok_Restrict => + return "restrict"; + when Tok_Restrict_Guarantee => + return "restrict_guarantee"; + when Tok_Sequence => + return "sequence"; -- AMS-VHDL when Tok_Across => @@ -412,24 +426,10 @@ package body Vhdl.Tokens is when Tok_Arobase => return "@"; - when Tok_Psl_Default => - return "default"; when Tok_Psl_Clock => return "clock"; - when Tok_Psl_Property => - return "property"; - when Tok_Psl_Sequence => - return "sequence"; when Tok_Psl_Endpoint => return "endpoint"; - when Tok_Psl_Assume => - return "assume"; - when Tok_Psl_Cover => - return "cover"; - when Tok_Psl_Restrict => - return "restrict"; - when Tok_Psl_Restrict_Guarantee => - return "restrict_guarantee"; when Tok_Psl_Const => return "const"; when Tok_Psl_Boolean => diff --git a/src/vhdl/vhdl-tokens.ads b/src/vhdl/vhdl-tokens.ads index f8e2dd14e..739134d2c 100644 --- a/src/vhdl/vhdl-tokens.ads +++ b/src/vhdl/vhdl-tokens.ads @@ -237,8 +237,15 @@ package Vhdl.Tokens is Tok_Protected, -- Added by vhdl 2008: + Tok_Assume, Tok_Context, + Tok_Cover, + Tok_Default, Tok_Parameter, + Tok_Property, + Tok_Restrict, + Tok_Restrict_Guarantee, + Tok_Sequence, -- AMS reserved words Tok_Across, @@ -256,15 +263,8 @@ package Vhdl.Tokens is Tok_Tolerance, -- PSL words - Tok_Psl_Default, Tok_Psl_Clock, - Tok_Psl_Property, - Tok_Psl_Sequence, Tok_Psl_Endpoint, - Tok_Psl_Assume, - Tok_Psl_Cover, - Tok_Psl_Restrict, - Tok_Psl_Restrict_Guarantee, Tok_Psl_Const, Tok_Psl_Boolean, -- cgit v1.2.3