From 6bc221560e88b7e5b6977ab0811f48f192db064a Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Wed, 1 Jul 2020 21:28:55 +0200 Subject: testsuite/gna: add tests for previous commit. --- testsuite/gna/bug0117/repro1.vhdl | 23 +++++++++++++++++++++++ testsuite/gna/bug0117/repro2.vhdl | 6 ++++++ testsuite/gna/bug0117/repro3.vhdl | 13 +++++++++++++ testsuite/gna/bug0117/repro4.vhdl | 26 ++++++++++++++++++++++++++ testsuite/gna/bug0117/repro5.vhdl | 24 ++++++++++++++++++++++++ testsuite/gna/bug0117/testsuite.sh | 14 ++++++++++++++ 6 files changed, 106 insertions(+) create mode 100644 testsuite/gna/bug0117/repro1.vhdl create mode 100644 testsuite/gna/bug0117/repro2.vhdl create mode 100644 testsuite/gna/bug0117/repro3.vhdl create mode 100644 testsuite/gna/bug0117/repro4.vhdl create mode 100644 testsuite/gna/bug0117/repro5.vhdl create mode 100755 testsuite/gna/bug0117/testsuite.sh diff --git a/testsuite/gna/bug0117/repro1.vhdl b/testsuite/gna/bug0117/repro1.vhdl new file mode 100644 index 000000000..5d8909b64 --- /dev/null +++ b/testsuite/gna/bug0117/repro1.vhdl @@ -0,0 +1,23 @@ +entity repro1 is +end repro1; + +architecture behav of repro1 is + type bv_array is array(natural range <>) of bit_vector; + type bv_array_ptr is access bv_array; + + procedure reshape (d : bv_array) is + constant word_len : natural := d(d'low)'length; + variable sym : bv_array_ptr; + begin + sym := new bv_array (0 to d'length - 1)(word_len - 1 downto 0); + sym.all := d; + end; + + signal s : bv_array(1 to 2)(7 downto 0); +begin + process + begin + reshape(s); + wait; + end process; +end behav; diff --git a/testsuite/gna/bug0117/repro2.vhdl b/testsuite/gna/bug0117/repro2.vhdl new file mode 100644 index 000000000..6a32765bc --- /dev/null +++ b/testsuite/gna/bug0117/repro2.vhdl @@ -0,0 +1,6 @@ +package repro2 is + type rec1 is record + wr : bit; + dat : bit_vector(7 downto 0); + end record; +end repro2; diff --git a/testsuite/gna/bug0117/repro3.vhdl b/testsuite/gna/bug0117/repro3.vhdl new file mode 100644 index 000000000..a17e82843 --- /dev/null +++ b/testsuite/gna/bug0117/repro3.vhdl @@ -0,0 +1,13 @@ +entity repro3 is +end; + +architecture behav of repro3 is + type rec1 is record + wr : bit; + dat : bit_vector(7 downto 0); + end record; + + signal s : rec1; +begin + s <= ('0', x"01"); +end behav; diff --git a/testsuite/gna/bug0117/repro4.vhdl b/testsuite/gna/bug0117/repro4.vhdl new file mode 100644 index 000000000..dcecbbd7f --- /dev/null +++ b/testsuite/gna/bug0117/repro4.vhdl @@ -0,0 +1,26 @@ +entity repro4 is +end repro4; + +architecture behav of repro4 is + type bv_array is array(natural range <>) of bit_vector; + type bv_array_ptr is access bv_array; +begin + process + variable count : natural := 0; + impure function seven return natural is + begin + report "seven"; + count := count + 1; + return 7; + end seven; + + subtype word_rng is natural range seven downto 0; + + subtype word_array is bv_array(open)(word_rng); + + subtype word_array4 is word_array(0 to 3); + begin + assert count = 1 severity failure; + wait; + end process; +end behav; diff --git a/testsuite/gna/bug0117/repro5.vhdl b/testsuite/gna/bug0117/repro5.vhdl new file mode 100644 index 000000000..3f3f8968e --- /dev/null +++ b/testsuite/gna/bug0117/repro5.vhdl @@ -0,0 +1,24 @@ +entity repro5 is +end repro5; + +architecture behav of repro5 is + type bv_array is array(natural range <>) of bit_vector; + type bv_array_ptr is access bv_array; +begin + process + variable count : natural := 0; + impure function seven return natural is + begin + report "seven"; + count := count + 1; + return 7; + end seven; + + subtype word_array is bv_array(open)(seven downto 0); + + subtype word_array4 is word_array(0 to 3); + begin + assert count = 1 severity failure; + wait; + end process; +end behav; diff --git a/testsuite/gna/bug0117/testsuite.sh b/testsuite/gna/bug0117/testsuite.sh new file mode 100755 index 000000000..d9bb64e30 --- /dev/null +++ b/testsuite/gna/bug0117/testsuite.sh @@ -0,0 +1,14 @@ +#! /bin/sh + +. ../../testenv.sh + +export GHDL_STD_FLAGS=--std=08 +analyze repro1.vhdl +elab_simulate repro1 + +analyze repro4.vhdl +elab_simulate repro4 + +clean + +echo "Test successful" -- cgit v1.2.3