From 73ef601ad03a28dace91be8a8055232874f45f63 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Sun, 17 Jan 2021 15:57:42 +0100 Subject: testsuite/pyunit/lsp/003errors: adjust testcase --- testsuite/pyunit/lsp/003errors/cmds.json | 2 +- testsuite/pyunit/lsp/003errors/replies.json | 95 ----------------------------- 2 files changed, 1 insertion(+), 96 deletions(-) diff --git a/testsuite/pyunit/lsp/003errors/cmds.json b/testsuite/pyunit/lsp/003errors/cmds.json index 20fabab7e..9d0ec527f 100644 --- a/testsuite/pyunit/lsp/003errors/cmds.json +++ b/testsuite/pyunit/lsp/003errors/cmds.json @@ -222,7 +222,7 @@ "uri": "file://pyunit/lsp/003errors/tc.vhdl", "languageId": "vhdl", "version": 1, - "text": "library ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_unsigned.all;\n\nentity tb is\nend tb;\n\narchitecture behav of tb is\n signal s : std_logic_vector(7 downto 0);\nbegin\n assert s /= x\"73\";\nend behav; \n" + "text": "library ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_unsigned.all;\n\nentity tb is\nend tb;\n\narchitecture behav of tb is\n signal s : std_logic_vector(7 downto 0);\nbegin\n s <= x\"73\";\nend behav; \n" } } }, diff --git a/testsuite/pyunit/lsp/003errors/replies.json b/testsuite/pyunit/lsp/003errors/replies.json index c4ec4dd04..9272ee7c8 100644 --- a/testsuite/pyunit/lsp/003errors/replies.json +++ b/testsuite/pyunit/lsp/003errors/replies.json @@ -43,101 +43,6 @@ }, "message": "use of synopsys package \"std_logic_unsigned\" needs the -fsynopsys option", "severity": 1 - }, - { - "source": "ghdl", - "range": { - "start": { - "line": 10, - "character": 13 - }, - "end": { - "line": 10, - "character": 13 - } - }, - "message": "operator \"/=\" is overloaded", - "severity": 1, - "relatedInformation": [ - { - "location": { - "uri": "file://pyunit/lsp/003errors/tc.vhdl", - "range": { - "start": { - "line": 10, - "character": 13 - }, - "end": { - "line": 10, - "character": 13 - } - } - }, - "message": "possible interpretations are:" - }, - { - "location": { - "uri": "file:///Users/gingold/devel/ghdl/lib/ghdl/src/synopsys/std_logic_unsigned.vhdl", - "range": { - "start": { - "line": 67, - "character": 13 - }, - "end": { - "line": 67, - "character": 13 - } - } - }, - "message": "function \"/=\" [std_logic_vector, std_logic_vector return boolean]" - }, - { - "location": { - "uri": "file:///Users/gingold/devel/ghdl/lib/ghdl/src/ieee/v93/std_logic_1164.vhdl", - "range": { - "start": { - "line": 89, - "character": 7 - }, - "end": { - "line": 89, - "character": 7 - } - } - }, - "message": "function \"/=\" [std_logic_vector, std_logic_vector return boolean]" - } - ] - }, - { - "source": "ghdl", - "range": { - "start": { - "line": 10, - "character": 13 - }, - "end": { - "line": 10, - "character": 13 - } - }, - "message": "(you may want to use the -fexplicit option)", - "severity": 1 - }, - { - "source": "ghdl", - "range": { - "start": { - "line": 8, - "character": 11 - }, - "end": { - "line": 8, - "character": 11 - } - }, - "message": "signal \"s\" is never referenced", - "severity": 2 } ] } -- cgit v1.2.3