From 7eae7370a101e4bb851394ce748f0fddf7fb3f2f Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Sun, 30 Apr 2023 10:08:45 +0200 Subject: testsuite/gna: add more tests for #2417 --- testsuite/gna/issue2417/repro3.vhdl | 73 ++++++++++++++++++++++++++++++++++++ testsuite/gna/issue2417/repro4.vhdl | 73 ++++++++++++++++++++++++++++++++++++ testsuite/gna/issue2417/repro5.vhdl | 73 ++++++++++++++++++++++++++++++++++++ testsuite/gna/issue2417/repro6.vhdl | 56 +++++++++++++++++++++++++++ testsuite/gna/issue2417/testsuite.sh | 8 ++-- 5 files changed, 279 insertions(+), 4 deletions(-) create mode 100644 testsuite/gna/issue2417/repro3.vhdl create mode 100644 testsuite/gna/issue2417/repro4.vhdl create mode 100644 testsuite/gna/issue2417/repro5.vhdl create mode 100644 testsuite/gna/issue2417/repro6.vhdl diff --git a/testsuite/gna/issue2417/repro3.vhdl b/testsuite/gna/issue2417/repro3.vhdl new file mode 100644 index 000000000..9021fcf70 --- /dev/null +++ b/testsuite/gna/issue2417/repro3.vhdl @@ -0,0 +1,73 @@ +package repro3_pkg is + type bit_vec_vec is array (natural range <>) of bit_vector; + + procedure p1(signal ack: bit; variable v: inout bit_vec_vec); + procedure p2(signal ack: bit; variable v: inout bit_vec_vec(1 downto 0)); + procedure p3(signal ack: bit; variable v: inout bit_vec_vec(open)(1 downto 0)); +end repro3_pkg; + +package body repro3_pkg is + procedure p1(signal ack: bit; variable v: inout bit_vec_vec) is + begin + wait until ack = '1'; + for i in v'range loop + v(i) := not v(i); + end loop; + end; + + procedure p2(signal ack: bit; variable v: inout bit_vec_vec(1 downto 0)) is + begin + wait until ack = '1'; + for i in v'range loop + v(i) := not v(i); + end loop; + end; + + procedure p3(signal ack: bit; + variable v: inout bit_vec_vec(open)(1 downto 0)) is + begin + wait until ack = '1'; + for i in v'range loop + v(i) := not v(i); + end loop; + end; +end; + +use work.repro3_pkg.all; + +entity repro3 is +end; + +architecture arch of repro3 is + signal ack1, ack2 : bit := '0'; +begin + process + variable v : bit_vec_vec(1 downto 0)(3 downto 0); + begin + v (0) := x"3"; + v (1) := x"c"; + p1 (ack1, v); + assert v(0) = x"c" and v(1) = x"3" severity failure; + wait; + end process; + + process + variable v : bit_vec_vec(1 downto 0)(3 downto 0); + begin + v (0) := x"1"; + v (1) := x"d"; + p1 (ack1, v); + assert v(0) = x"e" and v(1) = x"2" severity failure; + wait; + end process; + + process + begin + ack1 <= '1'; + wait for 1 ns; + ack2 <= '1'; + wait for 1 ns; + report "end of test"; + wait; + end process; +end; diff --git a/testsuite/gna/issue2417/repro4.vhdl b/testsuite/gna/issue2417/repro4.vhdl new file mode 100644 index 000000000..b4ca138b0 --- /dev/null +++ b/testsuite/gna/issue2417/repro4.vhdl @@ -0,0 +1,73 @@ +package repro4_pkg is + type bit_vec_vec is array (natural range <>) of bit_vector; + + procedure p1(signal ack: bit; variable v: inout bit_vec_vec); + procedure p2(signal ack: bit; variable v: inout bit_vec_vec(1 downto 0)); + procedure p3(signal ack: bit; variable v: inout bit_vec_vec(open)(1 downto 0)); +end repro4_pkg; + +package body repro4_pkg is + procedure p1(signal ack: bit; variable v: inout bit_vec_vec) is + begin + wait until ack = '1'; + for i in v'range loop + v(i) := not v(i); + end loop; + end; + + procedure p2(signal ack: bit; variable v: inout bit_vec_vec(1 downto 0)) is + begin + wait until ack = '1'; + for i in v'range loop + v(i) := not v(i); + end loop; + end; + + procedure p3(signal ack: bit; + variable v: inout bit_vec_vec(open)(1 downto 0)) is + begin + wait until ack = '1'; + for i in v'range loop + v(i) := not v(i); + end loop; + end; +end; + +use work.repro4_pkg.all; + +entity repro4 is +end; + +architecture arch of repro4 is + signal ack1, ack2 : bit := '0'; +begin + process + variable v : bit_vec_vec(1 downto 0)(3 downto 0); + begin + v (0) := x"3"; + v (1) := x"c"; + p2 (ack1, v); + assert v(0) = x"c" and v(1) = x"3" severity failure; + wait; + end process; + + process + variable v : bit_vec_vec(1 downto 0)(3 downto 0); + begin + v (0) := x"1"; + v (1) := x"d"; + p2 (ack1, v); + assert v(0) = x"e" and v(1) = x"2" severity failure; + wait; + end process; + + process + begin + ack1 <= '1'; + wait for 1 ns; + ack2 <= '1'; + wait for 1 ns; + report "end of test"; + wait; + end process; +end; diff --git a/testsuite/gna/issue2417/repro5.vhdl b/testsuite/gna/issue2417/repro5.vhdl new file mode 100644 index 000000000..8e2edbd34 --- /dev/null +++ b/testsuite/gna/issue2417/repro5.vhdl @@ -0,0 +1,73 @@ +package repro5_pkg is + type bit_vec_vec is array (natural range <>) of bit_vector; + + procedure p1(signal ack: bit; variable v: inout bit_vec_vec); + procedure p2(signal ack: bit; variable v: inout bit_vec_vec(1 downto 0)); + procedure p3(signal ack: bit; variable v: inout bit_vec_vec(open)(3 downto 0)); +end repro5_pkg; + +package body repro5_pkg is + procedure p1(signal ack: bit; variable v: inout bit_vec_vec) is + begin + wait until ack = '1'; + for i in v'range loop + v(i) := not v(i); + end loop; + end; + + procedure p2(signal ack: bit; variable v: inout bit_vec_vec(1 downto 0)) is + begin + wait until ack = '1'; + for i in v'range loop + v(i) := not v(i); + end loop; + end; + + procedure p3(signal ack: bit; + variable v: inout bit_vec_vec(open)(3 downto 0)) is + begin + wait until ack = '1'; + for i in v'range loop + v(i) := not v(i); + end loop; + end; +end; + +use work.repro5_pkg.all; + +entity repro5 is +end; + +architecture arch of repro5 is + signal ack1, ack2 : bit := '0'; +begin + process + variable v : bit_vec_vec(1 downto 0)(3 downto 0); + begin + v (0) := x"3"; + v (1) := x"c"; + p3 (ack1, v); + assert v(0) = x"c" and v(1) = x"3" severity failure; + wait; + end process; + + process + variable v : bit_vec_vec(1 downto 0)(3 downto 0); + begin + v (0) := x"1"; + v (1) := x"d"; + p3 (ack1, v); + assert v(0) = x"e" and v(1) = x"2" severity failure; + wait; + end process; + + process + begin + ack1 <= '1'; + wait for 1 ns; + ack2 <= '1'; + wait for 1 ns; + report "end of test"; + wait; + end process; +end; diff --git a/testsuite/gna/issue2417/repro6.vhdl b/testsuite/gna/issue2417/repro6.vhdl new file mode 100644 index 000000000..ea5efce03 --- /dev/null +++ b/testsuite/gna/issue2417/repro6.vhdl @@ -0,0 +1,56 @@ +package repro6_pkg is + type bit_vec_vec is array (natural range <>) of bit_vector; + +end repro6_pkg; + +use work.repro6_pkg.all; + +entity repro6_sub is + port (i : bit_vec_vec(1 downto 0); + o : out bit_vec_vec(1 downto 0)); +end; + +architecture behav of repro6_sub is +begin + process (i) + begin + for j in i'range loop + o(j) <= not i(j); + end loop; + end process; +end behav; + +use work.repro6_pkg.all; + +entity repro6 is +end; + +architecture behav of repro6 is + signal s1i, s1o, s2i, s2o : bit_vec_vec(1 downto 0)(3 downto 0); +begin + inst1 : entity work.repro6_sub + port map (i => s1i, o => s1o); + inst2 : entity work.repro6_sub + port map (i => s2i, o => s2o); + + process + begin + s1i (0) <= x"3"; + s1i (1) <= x"c"; + s2i (0) <= x"1"; + s2i (1) <= x"d"; + wait for 1 ns; + assert s1o(0) = x"c" and s1o(1) = x"3" severity failure; + assert s2o(0) = x"e" and s2o(1) = x"2" severity failure; + + s1i (0) <= x"4"; + s1i (1) <= x"a"; + s2i (0) <= x"5"; + s2i (1) <= x"6"; + wait for 1 ns; + assert s1o(0) = x"b" and s1o(1) = x"5" severity failure; + assert s2o(0) = x"a" and s2o(1) = x"9" severity failure; + + wait; + end process; +end; diff --git a/testsuite/gna/issue2417/testsuite.sh b/testsuite/gna/issue2417/testsuite.sh index fca1b9b9e..b319da51f 100755 --- a/testsuite/gna/issue2417/testsuite.sh +++ b/testsuite/gna/issue2417/testsuite.sh @@ -3,11 +3,11 @@ . ../../testenv.sh export GHDL_STD_FLAGS=--std=08 -analyze repro1.vhdl -elab_simulate repro1 -analyze repro2.vhdl -elab_simulate repro2 +for t in repro1 repro2 repro3 repro4 repro5 repro6; do + analyze $t.vhdl + elab_simulate $t +done clean -- cgit v1.2.3