From 8d1ab3e6d745c3314dab964f886f2f4cdb120310 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Tue, 30 Jun 2020 18:43:06 +0200
Subject: testsuite/synth: add a test for the previous commit.

---
 testsuite/synth/psl01/cover3.vhdl  | 20 ++++++++++++++++++++
 testsuite/synth/psl01/testsuite.sh |  3 +++
 2 files changed, 23 insertions(+)
 create mode 100644 testsuite/synth/psl01/cover3.vhdl

diff --git a/testsuite/synth/psl01/cover3.vhdl b/testsuite/synth/psl01/cover3.vhdl
new file mode 100644
index 000000000..59b70d7b6
--- /dev/null
+++ b/testsuite/synth/psl01/cover3.vhdl
@@ -0,0 +1,20 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cover3 is
+  port (
+    rst_n_i     : in    std_logic;
+    clk_i       : in    std_logic;
+    led0      : out   std_logic
+    );
+end cover3;
+
+architecture top of cover3 is
+  signal led : std_logic_vector(7 downto 0);
+  -- Although not expected (there should be rising_edge), this was crashing.
+  default clock is clk_i;
+begin
+  led0 <= led(0);
+
+  cover { led(0) = '1' };
+end architecture top;
diff --git a/testsuite/synth/psl01/testsuite.sh b/testsuite/synth/psl01/testsuite.sh
index 7707566f7..fe19e38c6 100755
--- a/testsuite/synth/psl01/testsuite.sh
+++ b/testsuite/synth/psl01/testsuite.sh
@@ -8,6 +8,9 @@ for f in restrict1 restrict2 assume1 assume2 assert1 cover1 cover2; do
   synth -fpsl $f.vhdl -e $f > syn_$f.vhdl
   analyze syn_$f.vhdl
 done
+
+synth_failure cover3.vhdl -e cover3
+
 clean
 
 echo "Test successful"
-- 
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