From 8d8b9d5449385b5609ec0d867ce32c545a814bb6 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sat, 13 Mar 2021 07:48:20 +0100
Subject: testsuite/synth: add a test for #1680

---
 testsuite/synth/issue1680/test_fail.vhdl | 33 ++++++++++++++++++++++++++++++++
 testsuite/synth/issue1680/testsuite.sh   |  7 +++++++
 2 files changed, 40 insertions(+)
 create mode 100644 testsuite/synth/issue1680/test_fail.vhdl
 create mode 100755 testsuite/synth/issue1680/testsuite.sh

diff --git a/testsuite/synth/issue1680/test_fail.vhdl b/testsuite/synth/issue1680/test_fail.vhdl
new file mode 100644
index 000000000..660558bce
--- /dev/null
+++ b/testsuite/synth/issue1680/test_fail.vhdl
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity test_fail is
+  port(
+    reset_n_i : in std_ulogic;
+    clock_i : in  std_ulogic;
+    value_o : out std_ulogic
+    );
+end test_fail;
+
+architecture beh of test_fail is
+  
+  signal value_s: std_ulogic;
+
+  attribute nomerge : string;
+  attribute nomerge of value_s : signal is "";
+  
+begin
+
+  regs: process (clock_i, reset_n_i)
+  begin
+    if reset_n_i = '0' then
+      value_s <= '0';
+    elsif rising_edge(clock_i) then
+      value_s <= not value_s;
+    end if;
+  end process;
+
+  value_o <= value_s;
+
+end architecture;
+
diff --git a/testsuite/synth/issue1680/testsuite.sh b/testsuite/synth/issue1680/testsuite.sh
new file mode 100755
index 000000000..9d823928f
--- /dev/null
+++ b/testsuite/synth/issue1680/testsuite.sh
@@ -0,0 +1,7 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth_only test_fail
+
+echo "Test successful"
-- 
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