From 966ffd5b0317e61f5b4e48c2e43889d055ddddcc Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Fri, 11 Oct 2019 06:57:27 +0200 Subject: vhdl: recognize conv_integer functions from std_logic_arith. --- python/libghdl/thin/std_names.py | 346 +++++++++++++++++---------------- python/libghdl/thin/vhdl/nodes.py | 4 + src/std_names.adb | 2 + src/std_names.ads | 10 +- src/synth/synth-oper.adb | 3 +- src/vhdl/vhdl-ieee-std_logic_arith.adb | 41 ++-- src/vhdl/vhdl-nodes.ads | 7 +- 7 files changed, 218 insertions(+), 195 deletions(-) diff --git a/python/libghdl/thin/std_names.py b/python/libghdl/thin/std_names.py index e9b7308b7..023bc2bdb 100644 --- a/python/libghdl/thin/std_names.py +++ b/python/libghdl/thin/std_names.py @@ -595,175 +595,177 @@ class Name: Rotate_Left = 809 Rotate_Right = 810 To_Bitvector = 811 - Conv_Unsigned = 812 - Math_Real = 813 - Ceil = 814 - Log2 = 815 - Last_Ieee = 815 - First_Directive = 816 - Define = 816 - Endif = 817 - Ifdef = 818 - Ifndef = 819 - Include = 820 - Timescale = 821 - Undef = 822 - Protect = 823 - Begin_Protected = 824 - End_Protected = 825 - Key_Block = 826 - Data_Block = 827 - Line = 828 - Celldefine = 829 - Endcelldefine = 830 - Default_Nettype = 831 - Resetall = 832 - Last_Directive = 832 - First_Systask = 833 - Bits = 833 - D_Root = 834 - D_Unit = 835 - Last_Systask = 835 - First_SV_Method = 836 - Size = 836 - Insert = 837 - Delete = 838 - Pop_Front = 839 - Pop_Back = 840 - Push_Front = 841 - Push_Back = 842 - Name = 843 - Len = 844 - Substr = 845 - Exists = 846 - Atoi = 847 - Itoa = 848 - Find = 849 - Find_Index = 850 - Find_First = 851 - Find_First_Index = 852 - Find_Last = 853 - Find_Last_Index = 854 - Num = 855 - Randomize = 856 - Pre_Randomize = 857 - Post_Randomize = 858 - Srandom = 859 - Get_Randstate = 860 - Set_Randstate = 861 - Seed = 862 - State = 863 - Last_SV_Method = 863 - First_BSV = 864 - uAction = 864 - uActionValue = 865 - BVI = 866 - uC = 867 - uCF = 868 - uE = 869 - uSB = 870 - uSBR = 871 - Action = 872 - Endaction = 873 - Actionvalue = 874 - Endactionvalue = 875 - Ancestor = 876 - Clocked_By = 877 - Default_Clock = 878 - Default_Reset = 879 - Dependencies = 880 - Deriving = 881 - Determines = 882 - Enable = 883 - Ifc_Inout = 884 - Input_Clock = 885 - Input_Reset = 886 - Instance = 887 - Endinstance = 888 - Let = 889 - Match = 890 - Method = 891 - Endmethod = 892 - Numeric = 893 - Output_Clock = 894 - Output_Reset = 895 - Par = 896 - Endpar = 897 - Path = 898 - Provisos = 899 - Ready = 900 - Reset_By = 901 - Rule = 902 - Endrule = 903 - Rules = 904 - Endrules = 905 - Same_Family = 906 - Schedule = 907 - Seq = 908 - Endseq = 909 - Typeclass = 910 - Endtypeclass = 911 - Valueof = 912 - uValueof = 913 - Last_BSV = 913 - First_Comment = 914 - Psl = 914 - Pragma = 915 - Last_Comment = 915 - First_PSL = 916 - A = 916 - Af = 917 - Ag = 918 - Ax = 919 - Abort = 920 - Assume_Guarantee = 921 - Before = 922 - Clock = 923 - E = 924 - Ef = 925 - Eg = 926 - Ex = 927 - Endpoint = 928 - Eventually = 929 - Fairness = 930 - Fell = 931 - Forall = 932 - G = 933 - Inf = 934 - Inherit = 935 - Never = 936 - Next_A = 937 - Next_E = 938 - Next_Event = 939 - Next_Event_A = 940 - Next_Event_E = 941 - Prev = 942 - Rose = 943 - Strong = 944 - W = 945 - Whilenot = 946 - Within = 947 - X = 948 - Last_PSL = 948 - First_Edif = 949 - Celltype = 959 - View = 960 - Viewtype = 961 - Direction = 962 - Contents = 963 - Net = 964 - Viewref = 965 - Cellref = 966 - Libraryref = 967 - Portinstance = 968 - Joined = 969 - Portref = 970 - Instanceref = 971 - Design = 972 - Designator = 973 - Owner = 974 - Member = 975 - Number = 976 - Rename = 977 - Userdata = 978 - Last_Edif = 978 + Conv_Signed = 812 + Conv_Unsigned = 813 + Conv_Integer = 814 + Math_Real = 815 + Ceil = 816 + Log2 = 817 + Last_Ieee = 817 + First_Directive = 818 + Define = 818 + Endif = 819 + Ifdef = 820 + Ifndef = 821 + Include = 822 + Timescale = 823 + Undef = 824 + Protect = 825 + Begin_Protected = 826 + End_Protected = 827 + Key_Block = 828 + Data_Block = 829 + Line = 830 + Celldefine = 831 + Endcelldefine = 832 + Default_Nettype = 833 + Resetall = 834 + Last_Directive = 834 + First_Systask = 835 + Bits = 835 + D_Root = 836 + D_Unit = 837 + Last_Systask = 837 + First_SV_Method = 838 + Size = 838 + Insert = 839 + Delete = 840 + Pop_Front = 841 + Pop_Back = 842 + Push_Front = 843 + Push_Back = 844 + Name = 845 + Len = 846 + Substr = 847 + Exists = 848 + Atoi = 849 + Itoa = 850 + Find = 851 + Find_Index = 852 + Find_First = 853 + Find_First_Index = 854 + Find_Last = 855 + Find_Last_Index = 856 + Num = 857 + Randomize = 858 + Pre_Randomize = 859 + Post_Randomize = 860 + Srandom = 861 + Get_Randstate = 862 + Set_Randstate = 863 + Seed = 864 + State = 865 + Last_SV_Method = 865 + First_BSV = 866 + uAction = 866 + uActionValue = 867 + BVI = 868 + uC = 869 + uCF = 870 + uE = 871 + uSB = 872 + uSBR = 873 + Action = 874 + Endaction = 875 + Actionvalue = 876 + Endactionvalue = 877 + Ancestor = 878 + Clocked_By = 879 + Default_Clock = 880 + Default_Reset = 881 + Dependencies = 882 + Deriving = 883 + Determines = 884 + Enable = 885 + Ifc_Inout = 886 + Input_Clock = 887 + Input_Reset = 888 + Instance = 889 + Endinstance = 890 + Let = 891 + Match = 892 + Method = 893 + Endmethod = 894 + Numeric = 895 + Output_Clock = 896 + Output_Reset = 897 + Par = 898 + Endpar = 899 + Path = 900 + Provisos = 901 + Ready = 902 + Reset_By = 903 + Rule = 904 + Endrule = 905 + Rules = 906 + Endrules = 907 + Same_Family = 908 + Schedule = 909 + Seq = 910 + Endseq = 911 + Typeclass = 912 + Endtypeclass = 913 + Valueof = 914 + uValueof = 915 + Last_BSV = 915 + First_Comment = 916 + Psl = 916 + Pragma = 917 + Last_Comment = 917 + First_PSL = 918 + A = 918 + Af = 919 + Ag = 920 + Ax = 921 + Abort = 922 + Assume_Guarantee = 923 + Before = 924 + Clock = 925 + E = 926 + Ef = 927 + Eg = 928 + Ex = 929 + Endpoint = 930 + Eventually = 931 + Fairness = 932 + Fell = 933 + Forall = 934 + G = 935 + Inf = 936 + Inherit = 937 + Never = 938 + Next_A = 939 + Next_E = 940 + Next_Event = 941 + Next_Event_A = 942 + Next_Event_E = 943 + Prev = 944 + Rose = 945 + Strong = 946 + W = 947 + Whilenot = 948 + Within = 949 + X = 950 + Last_PSL = 950 + First_Edif = 951 + Celltype = 961 + View = 962 + Viewtype = 963 + Direction = 964 + Contents = 965 + Net = 966 + Viewref = 967 + Cellref = 968 + Libraryref = 969 + Portinstance = 970 + Joined = 971 + Portref = 972 + Instanceref = 973 + Design = 974 + Designator = 975 + Owner = 976 + Member = 977 + Number = 978 + Rename = 979 + Userdata = 980 + Last_Edif = 980 diff --git a/python/libghdl/thin/vhdl/nodes.py b/python/libghdl/thin/vhdl/nodes.py index b77434aa7..700846bbb 100644 --- a/python/libghdl/thin/vhdl/nodes.py +++ b/python/libghdl/thin/vhdl/nodes.py @@ -1213,6 +1213,10 @@ class Iir_Predefined: Ieee_Std_Logic_Arith_Conv_Unsigned_Uns = 334 Ieee_Std_Logic_Arith_Conv_Unsigned_Sgn = 335 Ieee_Std_Logic_Arith_Conv_Unsigned_Log = 336 + Ieee_Std_Logic_Arith_Conv_Integer_Int = 337 + Ieee_Std_Logic_Arith_Conv_Integer_Uns = 338 + Ieee_Std_Logic_Arith_Conv_Integer_Sgn = 339 + Ieee_Std_Logic_Arith_Conv_Integer_Log = 340 Get_Kind = libghdl.vhdl__nodes__get_kind Get_Location = libghdl.vhdl__nodes__get_location diff --git a/src/std_names.adb b/src/std_names.adb index a19c9c6c0..d4722240c 100644 --- a/src/std_names.adb +++ b/src/std_names.adb @@ -647,7 +647,9 @@ package body Std_Names is Def ("rotate_left", Name_Rotate_Left); Def ("rotate_right", Name_Rotate_Right); Def ("to_bitvector", Name_To_Bitvector); + Def ("conv_signed", Name_Conv_Signed); Def ("conv_unsigned", Name_Conv_Unsigned); + Def ("conv_integer", Name_Conv_Integer); Def ("math_real", Name_Math_Real); Def ("ceil", Name_Ceil); Def ("log2", Name_Log2); diff --git a/src/std_names.ads b/src/std_names.ads index db3e82414..710c04814 100644 --- a/src/std_names.ads +++ b/src/std_names.ads @@ -728,10 +728,12 @@ package Std_Names is Name_Rotate_Left : constant Name_Id := Name_First_Ieee + 026; Name_Rotate_Right : constant Name_Id := Name_First_Ieee + 027; Name_To_Bitvector : constant Name_Id := Name_First_Ieee + 028; - Name_Conv_Unsigned : constant Name_Id := Name_First_Ieee + 029; - Name_Math_Real : constant Name_Id := Name_First_Ieee + 030; - Name_Ceil : constant Name_Id := Name_First_Ieee + 031; - Name_Log2 : constant Name_Id := Name_First_Ieee + 032; + Name_Conv_Signed : constant Name_Id := Name_First_Ieee + 029; + Name_Conv_Unsigned : constant Name_Id := Name_First_Ieee + 030; + Name_Conv_Integer : constant Name_Id := Name_First_Ieee + 031; + Name_Math_Real : constant Name_Id := Name_First_Ieee + 032; + Name_Ceil : constant Name_Id := Name_First_Ieee + 033; + Name_Log2 : constant Name_Id := Name_First_Ieee + 034; Name_Last_Ieee : constant Name_Id := Name_Log2; -- Verilog Directives. diff --git a/src/synth/synth-oper.adb b/src/synth/synth-oper.adb index 6754193aa..c08a85bb3 100644 --- a/src/synth/synth-oper.adb +++ b/src/synth/synth-oper.adb @@ -1075,7 +1075,8 @@ package body Synth.Oper is end if; end if; end; - when Iir_Predefined_Ieee_Numeric_Std_Toint_Uns_Nat => + when Iir_Predefined_Ieee_Numeric_Std_Toint_Uns_Nat + | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Integer_Uns => -- UNSIGNED to Natural. declare Int_Type : constant Type_Acc := diff --git a/src/vhdl/vhdl-ieee-std_logic_arith.adb b/src/vhdl/vhdl-ieee-std_logic_arith.adb index abb7218d2..28bf913a1 100644 --- a/src/vhdl/vhdl-ieee-std_logic_arith.adb +++ b/src/vhdl/vhdl-ieee-std_logic_arith.adb @@ -27,8 +27,23 @@ package body Vhdl.Ieee.Std_Logic_Arith is Unsigned_Type : Iir := Null_Iir; Signed_Type : Iir := Null_Iir; - type Arg_Kind is (Type_Signed, Type_Unsigned, Type_Int, - Type_Log, Type_Slv); + type Arg_Kind is (Type_Signed, Type_Unsigned, Type_Int, Type_Log, Type_Slv); + + subtype Conv_Arg_Kind is Arg_Kind range Type_Signed .. Type_Log; + type Conv_Pattern_Type is + array (Conv_Arg_Kind) of Iir_Predefined_Functions; + + Conv_Uns_Patterns : constant Conv_Pattern_Type := + (Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Sgn, + Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Uns, + Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Int, + Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Log); + + Conv_Int_Patterns : constant Conv_Pattern_Type := + (Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Integer_Sgn, + Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Integer_Uns, + Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Integer_Int, + Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Integer_Log); Error : exception; @@ -59,24 +74,14 @@ package body Vhdl.Ieee.Std_Logic_Arith is Arg1, Arg2 : Iir; Arg1_Kind, Arg2_Kind : Arg_Kind; - function Handle_Conv_Unsigned return Iir_Predefined_Functions is + function Handle_Conv (Pats : Conv_Pattern_Type) + return Iir_Predefined_Functions is begin if Arg2_Kind /= Type_Int then raise Error; end if; - case Arg1_Kind is - when Type_Int => - return Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Int; - when Type_Unsigned => - return Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Uns; - when Type_Signed => - return Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Sgn; - when Type_Log => - return Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Log; - when others => - raise Error; - end case; - end Handle_Conv_Unsigned; + return Pats (Arg1_Kind); + end Handle_Conv; Def : Iir_Predefined_Functions; begin @@ -146,13 +151,15 @@ package body Vhdl.Ieee.Std_Logic_Arith is case Get_Identifier (Decl) is when Name_Conv_Unsigned => - Def := Handle_Conv_Unsigned; + Def := Handle_Conv (Conv_Uns_Patterns); when others => null; end case; else -- Monadic function. case Get_Identifier (Decl) is + when Name_Conv_Integer => + Def := Conv_Int_Patterns (Arg1_Kind); when others => null; end case; diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index 44d25880d..bd25fb805 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -5110,7 +5110,12 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Int, Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Uns, Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Sgn, - Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Log + Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Log, + + Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Integer_Int, + Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Integer_Uns, + Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Integer_Sgn, + Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Integer_Log ); -- Return TRUE iff FUNC is a short-cut predefined function. -- cgit v1.2.3