From 9db35195bbafe7e7adf5dcf347fc1a30cc6873f8 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Mon, 16 Nov 2020 19:06:19 +0100
Subject: testsuite/synth: add a test for #1509

---
 testsuite/synth/issue1509/pass01.vhdl    | 11 +++++++++++
 testsuite/synth/issue1509/tb_pass01.vhdl | 23 +++++++++++++++++++++++
 testsuite/synth/issue1509/testsuite.sh   |  9 +++++++++
 3 files changed, 43 insertions(+)
 create mode 100644 testsuite/synth/issue1509/pass01.vhdl
 create mode 100644 testsuite/synth/issue1509/tb_pass01.vhdl
 create mode 100755 testsuite/synth/issue1509/testsuite.sh

diff --git a/testsuite/synth/issue1509/pass01.vhdl b/testsuite/synth/issue1509/pass01.vhdl
new file mode 100644
index 000000000..a7e780dd6
--- /dev/null
+++ b/testsuite/synth/issue1509/pass01.vhdl
@@ -0,0 +1,11 @@
+entity pass01 is
+    port (
+        i: in integer range -4 to 4;
+        o: out integer range -4 to 4
+    );
+end entity;
+
+architecture arch of pass01 is
+begin
+    o <= i;
+end architecture;
diff --git a/testsuite/synth/issue1509/tb_pass01.vhdl b/testsuite/synth/issue1509/tb_pass01.vhdl
new file mode 100644
index 000000000..a161dbb20
--- /dev/null
+++ b/testsuite/synth/issue1509/tb_pass01.vhdl
@@ -0,0 +1,23 @@
+entity tb_pass01 is
+end tb_pass01;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_pass01 is
+  subtype int_rng is integer range -4 to 4;
+  signal i, o: int_rng;
+begin
+  dut: entity work.pass01
+    port map (i, o);
+
+  process
+  begin
+    for k in int_rng loop
+      i <= k;
+      wait for 1 ns;
+      assert o = k severity failure;
+    end loop;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue1509/testsuite.sh b/testsuite/synth/issue1509/testsuite.sh
new file mode 100755
index 000000000..59f41a317
--- /dev/null
+++ b/testsuite/synth/issue1509/testsuite.sh
@@ -0,0 +1,9 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth_tb pass01
+
+clean
+
+echo "Test successful"
-- 
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