From ba2d9a39cb0c90c49f44d0d52258e8cc4920e15e Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Fri, 26 Mar 2021 18:37:16 +0100
Subject: testsuite/synth: Add a test case. For #1675

---
 testsuite/synth/issue1675/accum.vhdl      | 30 +++++++++++++++++
 testsuite/synth/issue1675/accumwr.vhdl    | 46 ++++++++++++++++++++++++++
 testsuite/synth/issue1675/patacc.vhdl     | 37 +++++++++++++++++++++
 testsuite/synth/issue1675/patgen.vhdl     | 38 ++++++++++++++++++++++
 testsuite/synth/issue1675/pkg.vhdl        | 16 +++++++++
 testsuite/synth/issue1675/tb_accum.vhdl   | 31 ++++++++++++++++++
 testsuite/synth/issue1675/tb_accumwr.vhdl | 41 +++++++++++++++++++++++
 testsuite/synth/issue1675/tb_patacc.vhdl  | 41 +++++++++++++++++++++++
 testsuite/synth/issue1675/tb_patgen.vhdl  | 54 +++++++++++++++++++++++++++++++
 testsuite/synth/issue1675/testsuite.sh    | 45 ++++++++++++++++++++++++++
 10 files changed, 379 insertions(+)
 create mode 100644 testsuite/synth/issue1675/accum.vhdl
 create mode 100644 testsuite/synth/issue1675/accumwr.vhdl
 create mode 100644 testsuite/synth/issue1675/patacc.vhdl
 create mode 100644 testsuite/synth/issue1675/patgen.vhdl
 create mode 100644 testsuite/synth/issue1675/pkg.vhdl
 create mode 100644 testsuite/synth/issue1675/tb_accum.vhdl
 create mode 100644 testsuite/synth/issue1675/tb_accumwr.vhdl
 create mode 100644 testsuite/synth/issue1675/tb_patacc.vhdl
 create mode 100644 testsuite/synth/issue1675/tb_patgen.vhdl
 create mode 100755 testsuite/synth/issue1675/testsuite.sh

diff --git a/testsuite/synth/issue1675/accum.vhdl b/testsuite/synth/issue1675/accum.vhdl
new file mode 100644
index 000000000..2e9fcf5d1
--- /dev/null
+++ b/testsuite/synth/issue1675/accum.vhdl
@@ -0,0 +1,30 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.pkg.all;
+
+entity accum is
+  port (
+    clk : std_logic;
+    b_i : bus_rec_out_t;
+    res : out std_logic_vector(15 downto 0));
+end accum;
+
+architecture behav of accum is
+  signal acc : unsigned(15 downto 0);
+begin
+  process (clk) is
+  begin
+    if rising_edge(clk) then
+      if b_i.rst = '1' then
+        acc <= (others => '0');
+      elsif b_i.stb = '1' then
+        acc <= acc + unsigned(b_i.dat);
+      end if;
+    end if;
+  end process;
+
+  res <= std_logic_vector(acc);
+end behav;
+
diff --git a/testsuite/synth/issue1675/accumwr.vhdl b/testsuite/synth/issue1675/accumwr.vhdl
new file mode 100644
index 000000000..d12f24027
--- /dev/null
+++ b/testsuite/synth/issue1675/accumwr.vhdl
@@ -0,0 +1,46 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.pkg.all;
+
+entity accumwr is
+  port (
+    clk : std_logic;
+    rst : std_logic;
+    en : std_logic;
+    res : out std_logic_vector(15 downto 0));
+end accumwr;
+
+architecture behav of accumwr is
+  signal cnt : unsigned(1 downto 0);
+  signal bo : bus_rec_out_t;
+begin
+  with cnt select
+    bo.dat <= x"01" when "00",
+    x"02" when "01",
+    x"03" when "10",
+    x"05" when "11",
+    x"00" when others;
+
+  bo.rst <= rst;
+  bo.stb <= en;
+
+  process (clk) is
+  begin
+    if rising_edge(clk) then
+      if rst = '1' then
+        cnt <= "00";
+      elsif en = '1' then
+        cnt <= cnt + 1;
+      end if;
+    end if;
+  end process;
+
+  inst_accum: entity work.accum
+    port map (
+      clk => clk,
+      b_i => bo,
+      res => res);
+end behav;
+
diff --git a/testsuite/synth/issue1675/patacc.vhdl b/testsuite/synth/issue1675/patacc.vhdl
new file mode 100644
index 000000000..ecb6b0717
--- /dev/null
+++ b/testsuite/synth/issue1675/patacc.vhdl
@@ -0,0 +1,37 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.pkg.all;
+
+entity patacc is
+  port (
+    clk : std_logic;
+    rst : std_logic;
+    res : out std_logic_vector(15 downto 0));
+end patacc;
+
+architecture behav of patacc is
+  signal bo : bus_rec_out_t;
+  signal acc : unsigned(15 downto 0);
+begin
+  inst: entity work.patgen
+    port map (
+      clk => clk,
+      rst => rst,
+      bo => bo);
+
+  process (clk) is
+  begin
+    if rising_edge(clk) then
+      if bo.rst = '1' then
+        acc <= (others => '0');
+      elsif bo.stb = '1' then
+        acc <= acc + unsigned(bo.dat);
+      end if;
+    end if;
+  end process;
+
+  res <= std_logic_vector(acc);
+end behav;
+
diff --git a/testsuite/synth/issue1675/patgen.vhdl b/testsuite/synth/issue1675/patgen.vhdl
new file mode 100644
index 000000000..820185021
--- /dev/null
+++ b/testsuite/synth/issue1675/patgen.vhdl
@@ -0,0 +1,38 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.pkg.all;
+
+entity patgen is
+  port (
+    clk : std_logic;
+    rst : std_logic;
+    bo : out bus_rec_out_t);
+end patgen;
+
+architecture behav of patgen is
+  signal cnt : unsigned(1 downto 0);
+begin
+  with cnt select
+    bo.dat <= x"01" when "00",
+    x"02" when "01",
+    x"03" when "10",
+    x"05" when "11",
+    x"00" when others;
+
+  bo.rst <= rst;
+  bo.stb <= not rst;
+
+  process (clk) is
+  begin
+    if rising_edge(clk) then
+      if rst = '1' then
+        cnt <= "00";
+      else
+        cnt <= cnt + 1;
+      end if;
+    end if;
+  end process;
+end behav;
+
diff --git a/testsuite/synth/issue1675/pkg.vhdl b/testsuite/synth/issue1675/pkg.vhdl
new file mode 100644
index 000000000..797995576
--- /dev/null
+++ b/testsuite/synth/issue1675/pkg.vhdl
@@ -0,0 +1,16 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+package pkg is
+  type bus_rec_out_t is record
+    dat : std_logic_vector(7 downto 0);
+    stb : std_logic;
+    rst : std_logic;
+  end record;
+
+  type bus_rec_in_t is record
+    dat : std_logic_vector(7 downto 0);
+    stb : std_logic;
+  end record;
+end pkg;
+
diff --git a/testsuite/synth/issue1675/tb_accum.vhdl b/testsuite/synth/issue1675/tb_accum.vhdl
new file mode 100644
index 000000000..325072a09
--- /dev/null
+++ b/testsuite/synth/issue1675/tb_accum.vhdl
@@ -0,0 +1,31 @@
+entity tb_accum is
+end tb_accum;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.pkg.all;
+
+architecture behav of tb_accum is
+  signal clk : std_logic;
+  signal bi : bus_rec_out_t;
+  signal res : std_logic_vector(15 downto 0);
+begin
+  dut: entity work.accum
+    port map (clk, bi, res);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    bi <= (dat => x"00", stb => '0', rst => '1');
+    pulse;
+    assert res = x"0000" severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue1675/tb_accumwr.vhdl b/testsuite/synth/issue1675/tb_accumwr.vhdl
new file mode 100644
index 000000000..ead0fe966
--- /dev/null
+++ b/testsuite/synth/issue1675/tb_accumwr.vhdl
@@ -0,0 +1,41 @@
+entity tb_accumwr is
+end tb_accumwr;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.pkg.all;
+
+architecture behav of tb_accumwr is
+  signal clk : std_logic;
+  signal rst : std_logic;
+  signal en : std_logic;
+  signal res : std_logic_vector(15 downto 0);
+begin
+  dut: entity work.accumwr
+    port map (clk, rst, en, res);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    rst <= '1';
+    en <= '0';
+    pulse;
+    assert res = x"0000" severity failure;
+
+    rst <= '0';
+    pulse;
+    assert res = x"0000" severity failure;
+
+    en <= '1';
+    pulse;
+    assert res = x"0001" severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue1675/tb_patacc.vhdl b/testsuite/synth/issue1675/tb_patacc.vhdl
new file mode 100644
index 000000000..15468118c
--- /dev/null
+++ b/testsuite/synth/issue1675/tb_patacc.vhdl
@@ -0,0 +1,41 @@
+entity tb_patacc is
+end tb_patacc;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.pkg.all;
+
+architecture behav of tb_patacc is
+  signal clk : std_logic;
+  signal rst : std_logic;
+  signal res : std_logic_vector(15 downto 0);
+begin
+  dut: entity work.patacc
+    port map (clk, rst, res);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    rst <= '1';
+    pulse;
+    assert res = x"0000" severity failure;
+
+    rst <= '0';
+    pulse;
+    assert res = x"0001" severity failure;
+
+    pulse;
+    assert res = x"0003" severity failure;
+
+    pulse;
+    assert res = x"0006" severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue1675/tb_patgen.vhdl b/testsuite/synth/issue1675/tb_patgen.vhdl
new file mode 100644
index 000000000..3b0586ef0
--- /dev/null
+++ b/testsuite/synth/issue1675/tb_patgen.vhdl
@@ -0,0 +1,54 @@
+entity tb_patgen is
+end tb_patgen;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.pkg.all;
+
+architecture behav of tb_patgen is
+  signal clk : std_logic;
+  signal rst : std_logic;
+  signal bo : bus_rec_out_t;
+begin
+  dut: entity work.patgen
+    port map (clk, rst, bo);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    rst <= '1';
+    pulse;
+    assert bo.dat = x"01" severity failure;
+    assert bo.rst = '1' severity failure;
+    assert bo.stb = '0' severity failure;
+
+    rst <= '0';
+    pulse;
+    assert bo.dat = x"02" severity failure;
+    assert bo.rst = '0' severity failure;
+    assert bo.stb = '1' severity failure;
+
+    pulse;
+    assert bo.dat = x"03" severity failure;
+    assert bo.rst = '0' severity failure;
+    assert bo.stb = '1' severity failure;
+
+    pulse;
+    assert bo.dat = x"05" severity failure;
+    assert bo.rst = '0' severity failure;
+    assert bo.stb = '1' severity failure;
+
+    pulse;
+    assert bo.dat = x"01" severity failure;
+    assert bo.rst = '0' severity failure;
+    assert bo.stb = '1' severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue1675/testsuite.sh b/testsuite/synth/issue1675/testsuite.sh
new file mode 100755
index 000000000..23b988cc0
--- /dev/null
+++ b/testsuite/synth/issue1675/testsuite.sh
@@ -0,0 +1,45 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+# accum
+analyze pkg.vhdl accum.vhdl tb_accum.vhdl
+elab_simulate tb_accum
+clean
+
+synth pkg.vhdl accum.vhdl -e > syn_accum.vhdl
+analyze pkg.vhdl syn_accum.vhdl tb_accum.vhdl
+elab_simulate tb_accum --ieee-asserts=disable-at-0 --assert-level=error
+clean
+
+# accumwr
+analyze pkg.vhdl accum.vhdl accumwr.vhdl tb_accumwr.vhdl
+elab_simulate tb_accumwr
+clean
+
+synth pkg.vhdl accum.vhdl accumwr.vhdl -e > syn_accumwr.vhdl
+analyze pkg.vhdl syn_accumwr.vhdl tb_accumwr.vhdl
+elab_simulate tb_accumwr --ieee-asserts=disable-at-0 --assert-level=error
+clean
+
+# patgen
+analyze pkg.vhdl patgen.vhdl tb_patgen.vhdl
+elab_simulate tb_patgen
+clean
+
+synth pkg.vhdl patgen.vhdl -e > syn_patgen.vhdl
+analyze pkg.vhdl syn_patgen.vhdl tb_patgen.vhdl
+elab_simulate tb_patgen --ieee-asserts=disable-at-0 --assert-level=error
+clean
+
+# patacc
+analyze pkg.vhdl patgen.vhdl patacc.vhdl tb_patacc.vhdl
+elab_simulate tb_patacc
+clean
+
+synth pkg.vhdl patgen.vhdl patacc.vhdl -e > syn_patacc.vhdl
+analyze pkg.vhdl syn_patacc.vhdl tb_patacc.vhdl
+elab_simulate tb_patacc --ieee-asserts=disable-at-0 --assert-level=error
+clean
+
+echo "Test successful"
-- 
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