From f18054335bcf3b67731d61ee53e7142ac39ed6f7 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <gingold@adacore.com>
Date: Thu, 7 Jan 2016 19:48:46 +0100
Subject: Add reproducer for issue14

---
 testsuite/gna/issue14/repro.vhdl   | 20 ++++++++++++++++++++
 testsuite/gna/issue14/repro1.vhdl  | 10 ++++++++++
 testsuite/gna/issue14/testsuite.sh | 18 ++++++++++++++++++
 3 files changed, 48 insertions(+)
 create mode 100644 testsuite/gna/issue14/repro.vhdl
 create mode 100644 testsuite/gna/issue14/repro1.vhdl
 create mode 100755 testsuite/gna/issue14/testsuite.sh

diff --git a/testsuite/gna/issue14/repro.vhdl b/testsuite/gna/issue14/repro.vhdl
new file mode 100644
index 000000000..4dc747f1e
--- /dev/null
+++ b/testsuite/gna/issue14/repro.vhdl
@@ -0,0 +1,20 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity repro is
+end repro;
+
+architecture behav of repro is
+begin
+  process
+    variable z : std_ulogic_vector (1 to 2) := "00";
+    variable r : std_ulogic;
+  begin
+    r := z ?= "LL";
+    assert r = '1';
+    z := "--";
+    r := z ?= "00";  -- One warning
+    r := z ?= "--";  -- Two warning
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/gna/issue14/repro1.vhdl b/testsuite/gna/issue14/repro1.vhdl
new file mode 100644
index 000000000..468b6515c
--- /dev/null
+++ b/testsuite/gna/issue14/repro1.vhdl
@@ -0,0 +1,10 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity repro is
+end repro;
+
+architecture behav of repro is
+begin
+  assert std_ulogic_vector'("LL") ?= "00";
+end behav;
diff --git a/testsuite/gna/issue14/testsuite.sh b/testsuite/gna/issue14/testsuite.sh
new file mode 100755
index 000000000..7b441358b
--- /dev/null
+++ b/testsuite/gna/issue14/testsuite.sh
@@ -0,0 +1,18 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=--std=08
+analyze repro.vhdl
+elab_simulate repro 2>&1 | tee log.txt
+
+if test `grep -c assert log.txt` -ne 2; then
+    exit 1
+else
+    echo "Expected number of warnings"
+fi
+
+clean
+rm log.txt
+
+echo "Test successful"
-- 
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