From 7b2b91900e8217fd75fcc755f14c5f098662f1f8 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sat, 4 Mar 2017 18:47:08 +0100 Subject: Fixed typos, indentation and headline underlining. --- doc/about.rst | 32 +++++++++++++++++--------------- 1 file changed, 17 insertions(+), 15 deletions(-) (limited to 'doc/about.rst') diff --git a/doc/about.rst b/doc/about.rst index 9b11ed5bf..ee0ced2e0 100644 --- a/doc/about.rst +++ b/doc/about.rst @@ -1,12 +1,12 @@ -.. include:: shieldswho.txt +.. include:: shieldswho.inc About GHDL -############ +########## .. _INTRO:VHDL: What is `VHDL`? -============== +=============== :wikipedia:`VHDL ` is an acronym for Very High Speed Integrated Circuit (:wikipedia:`VHSIC `) Hardware Description Language (:wikipedia:`HDL `), which is a programming language used to describe a logic circuit by function, data flow behavior, or structure. @@ -16,12 +16,13 @@ However, VHDL was not designed as a general purpose language but as an `HDL`. As Like a program written in any other language, a VHDL program can be executed. Since VHDL is used to model designs, the term :dfn:`simulation` is often used instead of `execution`, with the same meaning. At the same time, like a design written in another `HDL`, a set of VHDL sources can be transformed with a :dfn:`synthesis tool` into a netlist, that is, a detailed gate-level implementation. -The development of VHDL started in 1983 and the standard is named `IEEE `_ `1076`. Four revisions exist: `1987 `_, `1993 `_, `2002 `_ and `2008 `_. The standarization is handled by the VHDL Analysis and Standardization Group (`VASG/P1076 `_). +The development of VHDL started in 1983 and the standard is named `IEEE `_ `1076`. Four revisions exist: `1987 `_, `1993 `_, `2002 `_ and `2008 `_. The standardization is handled by the VHDL Analysis and Standardization Group (`VASG/P1076 `_). + .. _INTRO:GHDL: What is GHDL? -============== +============= `GHDL` is a shorthand for `G Hardware Design Language` (currently, `G` has no meaning). It is a VHDL compiler that can execute (nearly) any VHDL program. GHDL is *not* a synthesis tool: you cannot create a netlist with GHDL (yet). @@ -29,12 +30,13 @@ Unlike some other simulators, GHDL is a compiler: it directly translates a VHDL GHDL can use multiple back-ends, i.e. code generators, (`GCC `_, `LLVM `_ or :wikipedia:`x86 `/:wikipedia:`i386 ` only, a built-in one) and runs on :wikipedia:`GNU/Linux `, :wikipedia:`Windows ` |trade| and :wikipedia:`macOS ` |trade| , both on x86 and on x86_64. -The current version of GHDL does not contain any graphical viewer: you cannot see signal waves. You can still check the behaviour of your design with a test bench. Moreover, the current version can produce a `GHW `_, :wikipedia:`VCD ` or `FST` files which can be viewed with a :wikipedia:`waveform viewer `, such as `GtkWave `_. +The current version of GHDL does not contain any graphical viewer: you cannot see signal waves. You can still check the behavior of your design with a test bench. Moreover, the current version can produce a `GHW `_, :wikipedia:`VCD ` or `FST` files which can be viewed with a :wikipedia:`waveform viewer `, such as `GtkWave `_. GHDL aims at implementing VHDL as defined by `IEEE 1076 `_. It supports the `1987 `_, `1993 `_ and `2002 `_ revisions and, partially, the latest, `2008 `_. :wikipedia:`PSL ` is also partially supported. Several third party projects are supported: `VUnit `_, `OSVVM `_, `cocotb `_ (through the `VPI interface `_), ... + .. _INTRO:WHO: Who uses GHDL? @@ -42,12 +44,12 @@ Who uses GHDL? .. container:: whouses - +-------------------+--------------------+---------------------------------------------------+----------------------------------------------------------------+ - | Project hub | Documentation | Name | Brief description | - +===================+====================+===================================================+================================================================+ - | |SHIELD:gh-poc| | |SHIELD:rtd-poc| | `PoC-Library `_ | A Vendor-Independent, Open-Source IP Core and Utility Library. | - +-------------------+--------------------+---------------------------------------------------+----------------------------------------------------------------+ - | |SHIELD:gh-vunit| | |SHIELD:doc-vunit| | `VUnit `_ | A unit testing framework for VHDL/SystemVerilog | - +-------------------+--------------------+---------------------------------------------------+----------------------------------------------------------------+ - | |SHIELD:gl-p1076| | |SHIELD:tw-p1076| | `IEEE P1076 WG `_ | IEEE P1076 Working Group [VASG] | - +-------------------+--------------------+---------------------------------------------------+----------------------------------------------------------------+ + +-------------------+--------------------+---------------------------------------------------+----------------------------------------------------------------+ + | Project hub | Documentation | Name | Brief description | + +===================+====================+===================================================+================================================================+ + | |SHIELD:gh-poc| | |SHIELD:rtd-poc| | `PoC-Library `_ | A Vendor-Independent, Open-Source IP Core and Utility Library. | + +-------------------+--------------------+---------------------------------------------------+----------------------------------------------------------------+ + | |SHIELD:gh-vunit| | |SHIELD:doc-vunit| | `VUnit `_ | A unit testing framework for VHDL/SystemVerilog | + +-------------------+--------------------+---------------------------------------------------+----------------------------------------------------------------+ + | |SHIELD:gl-p1076| | |SHIELD:tw-p1076| | `IEEE P1076 WG `_ | IEEE P1076 Working Group [VASG] | + +-------------------+--------------------+---------------------------------------------------+----------------------------------------------------------------+ -- cgit v1.2.3