From 75ef931f4a7a0a4f3ddca1727d6f63ea6f4d2482 Mon Sep 17 00:00:00 2001 From: umarcor Date: Tue, 5 Jan 2021 22:34:14 +0100 Subject: doc: reorganise and update --- doc/quick_start/simulation/adder/adder.vhdl | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 doc/quick_start/simulation/adder/adder.vhdl (limited to 'doc/quick_start/simulation/adder/adder.vhdl') diff --git a/doc/quick_start/simulation/adder/adder.vhdl b/doc/quick_start/simulation/adder/adder.vhdl new file mode 100644 index 000000000..cf60e8fbe --- /dev/null +++ b/doc/quick_start/simulation/adder/adder.vhdl @@ -0,0 +1,14 @@ +entity adder is + -- `i0`, `i1`, and the carry-in `ci` are inputs of the adder. + -- `s` is the sum output, `co` is the carry-out. + port (i0, i1 : in bit; ci : in bit; s : out bit; co : out bit); +end adder; + +architecture rtl of adder is +begin + -- This full-adder architecture contains two concurrent assignments. + -- Compute the sum. + s <= i0 xor i1 xor ci; + -- Compute the carry. + co <= (i0 and i1) or (i0 and ci) or (i1 and ci); +end rtl; -- cgit v1.2.3