From 28d9ddf0e2aff8fe6937949f54285cae9ee478a7 Mon Sep 17 00:00:00 2001
From: 1138-4EB <1138-4EB@users.noreply.github.com>
Date: Thu, 2 Mar 2017 00:24:57 +0100
Subject: =?UTF-8?q?Add=20raw=20sources=20of=20tutorial=20'How=20to=20simul?=
=?UTF-8?q?ate=20an=20UART=20VHDL=20code=20with=20ghdl}'=20by=20'Ren=C3=A9?=
=?UTF-8?q?=20Do=C3=9F'?=
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doc/using/UART_srcs/capitalisation/Zeichnung.svg | 225 +++++++++++++++++++++
.../UART_srcs/capitalisation/capitalisation.png | Bin 0 -> 48212 bytes
.../UART_srcs/capitalisation/capitalisation.vhd | 51 +++++
doc/using/UART_srcs/capitalisation/makefile | 18 ++
.../UART_srcs/capitalisation/tb_capitalisation.vhd | 89 ++++++++
.../capitalisation/top_capitalisation.vhd | 126 ++++++++++++
doc/using/UART_srcs/capitalisation/zeichnung.png | Bin 0 -> 15065 bytes
7 files changed, 509 insertions(+)
create mode 100644 doc/using/UART_srcs/capitalisation/Zeichnung.svg
create mode 100644 doc/using/UART_srcs/capitalisation/capitalisation.png
create mode 100644 doc/using/UART_srcs/capitalisation/capitalisation.vhd
create mode 100644 doc/using/UART_srcs/capitalisation/makefile
create mode 100644 doc/using/UART_srcs/capitalisation/tb_capitalisation.vhd
create mode 100644 doc/using/UART_srcs/capitalisation/top_capitalisation.vhd
create mode 100644 doc/using/UART_srcs/capitalisation/zeichnung.png
(limited to 'doc/using/UART_srcs/capitalisation')
diff --git a/doc/using/UART_srcs/capitalisation/Zeichnung.svg b/doc/using/UART_srcs/capitalisation/Zeichnung.svg
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index 000000000..e64d02ab5
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@@ -0,0 +1,225 @@
+
+
+
+
diff --git a/doc/using/UART_srcs/capitalisation/capitalisation.png b/doc/using/UART_srcs/capitalisation/capitalisation.png
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index 000000000..5b6dcbc37
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diff --git a/doc/using/UART_srcs/capitalisation/capitalisation.vhd b/doc/using/UART_srcs/capitalisation/capitalisation.vhd
new file mode 100644
index 000000000..e904eda95
--- /dev/null
+++ b/doc/using/UART_srcs/capitalisation/capitalisation.vhd
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+-- loopback engine
+----------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use ieee.numeric_std.all;
+
+entity capitalisation is
+ port(
+ clk : in std_logic;
+ reset : in std_logic;
+ --in
+ rdata : in std_logic_vector(7 downto 0);
+ rd_en : in std_logic;
+ rd : out std_logic;
+ --out
+ wdata : out std_logic_vector(7 downto 0);
+ wr_en : in std_logic;
+ wr : out std_logic
+ );
+end;
+
+architecture Behavioral of capitalisation is
+
+
+
+begin
+
+
+ process(clk)
+ begin
+ wr<='0';
+ rd<='0';
+ if wr_en='1' and rd_en ='1' then
+ wr<='1';
+ rd<='1';
+ if (unsigned(rdata)>X"60") and
+ (unsigned(rdata) board_clk_freq,
+ baudrate =>115200)
+ port map(
+ board_clk => board_clk,
+ reset => reset,
+ rx => rx,
+ tx => tx );
+
+ process
+ begin
+ wait for 80000 ns;
+ tx_char(RX, '$', 115200);
+ tx_char(RX, 'g', 115200);
+ tx_char(RX, '#', 115200);
+ wait for 50 us;
+ tx_char(RX, 'b', 115200);
+ tx_char(RX, 'c', 115200);
+ wait; -- will wait forever
+ end process;
+
+ -- Clock process definitions
+ board_clk_process : process
+ begin
+ board_clk <= '0';
+ wait for board_clk_period/2;
+ board_clk <= '1';
+ wait for board_clk_period/2;
+ end process;
+
+ -- Stimulus process
+ process
+ begin
+ reset <= '1';
+ wait for 100 ns;
+ reset <='0';
+ wait;
+ end process;
+
+end;
diff --git a/doc/using/UART_srcs/capitalisation/top_capitalisation.vhd b/doc/using/UART_srcs/capitalisation/top_capitalisation.vhd
new file mode 100644
index 000000000..01c8e3585
--- /dev/null
+++ b/doc/using/UART_srcs/capitalisation/top_capitalisation.vhd
@@ -0,0 +1,126 @@
+-- top_capitalisation.vhd
+----------------------------------------------------------------------
+
+-- top_capitalisation
+-- |
+-- + capitalisation
+-- + UART_8N1_RX
+-- + UART_8N1_TX
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity top_capitalisation is
+ generic (clk_freq : integer;
+ baudrate : integer);
+ port(
+ board_clk : in std_logic ;
+ reset : in std_logic ;
+ rx : in std_logic ;
+ tx : out std_logic );
+end top_capitalisation;
+
+architecture behavior of top_capitalisation is
+ signal rd_en : std_logic;
+ signal rdata : std_logic_vector (7 downto 0);
+ signal rd : std_logic;
+
+ signal wr_en : std_logic;
+ signal wdata : std_logic_vector (7 downto 0);
+ signal wr : std_logic;
+
+component capitalisation is
+ port(
+ clk : in std_logic;
+ reset : in std_logic;
+ --in
+ rdata : in std_logic_vector(7 downto 0);
+ rd_en : in std_logic;
+ rd : out std_logic;
+ --out
+ wdata : out std_logic_vector(7 downto 0);
+ wr_en : in std_logic;
+ wr : out std_logic
+ );
+end component;
+
+component UART_8N1_RX is
+ generic (clk_freq : integer;
+ baudrate : integer);
+ port(
+ clk : in std_logic;
+ reset : in std_logic;
+ --8bit interface
+ rdata : out std_logic_vector(7 downto 0);
+ rd : in std_logic;
+ rd_en : out std_logic;
+ --physical wire RX
+ rx : in std_logic
+ );
+end component;
+
+component UART_8N1_TX is
+ generic(
+ clk_freq : integer;
+ baudrate : integer;
+ addr_depth : integer:=5);
+ port(
+ clk : in std_logic;
+ reset : in std_logic;
+ --8bit interface
+ wdata : in std_logic_vector(7 downto 0);
+ wr : in std_logic;
+ wr_en : out std_logic;
+
+ --physical wire
+ tx : out std_logic);
+end component;
+
+
+begin
+
+UART_RX:UART_8N1_RX
+ generic map (
+ clk_freq => clk_freq,
+ baudrate =>115200)
+ port map(
+ clk => board_clk,
+ reset => reset,
+ rdata => rdata,
+ rd => rd,
+ rd_en => rd_en,
+ --physical wire RX
+ rx => rx
+ );
+
+trans: capitalisation
+ port map(
+ clk => board_clk,
+ reset => reset,
+ --in
+ rdata => rdata,
+ rd_en => rd_en,
+ rd => rd,
+ --out
+ wdata => wdata,
+ wr_en => wr_en,
+ wr => wr
+ );
+
+UART_TX: UART_8N1_TX
+ generic map(
+ clk_freq => clk_freq,
+ baudrate => 115200)
+ port map(
+ clk => board_clk,
+ reset => reset,
+ --8bit interface
+ wdata => wdata,
+ wr => wr,
+ wr_en => wr_en,
+
+ --physical wire TX
+ tx => tx
+ );
+end;
diff --git a/doc/using/UART_srcs/capitalisation/zeichnung.png b/doc/using/UART_srcs/capitalisation/zeichnung.png
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index 000000000..f51a0fbdd
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