From 199dd673c7c68c40f0ab672869a8b8b04c349860 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Wed, 28 Apr 2021 21:23:34 +0200 Subject: doc: document --out=verilog for synth --- doc/using/Synthesis.rst | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'doc/using') diff --git a/doc/using/Synthesis.rst b/doc/using/Synthesis.rst index e5f9554cc..d3968fe67 100644 --- a/doc/using/Synthesis.rst +++ b/doc/using/Synthesis.rst @@ -87,13 +87,16 @@ In addition to those options, there are some synthesis specific options. $ ghdl --synth --std=08 -gDEPTH=12 [library.]top_unit [arch] -.. option:: --out= +.. option:: --out= * **vhdl** *(default)*: equivalent to ``raw-vhdl``, but the original top-level unit is preserved unmodified, so the synthesized design can be simulated with the same testbench. - * **raw-vhdl**: all statements are converted to a simple VHDL 1993 netlist, for allowing instantiation in other - synthesis tools without modern VHDL support. + * **raw-vhdl**: all statements are converted to a simple VHDL 1993 + netlist, for allowing instantiation in other synthesis tools + without modern VHDL support. + + * **verilog**: generate a verilog netlist. * **dot**: generate a graphviz dot diagram of the netlist AST. -- cgit v1.2.3