From e95d45e41d32c0d73179cea22c8b3ea812eafb41 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Thu, 13 Apr 2023 23:44:29 +0200 Subject: Reworking symbols. --- pyGHDL/dom/Concurrent.py | 32 +++++++++++++------------------- 1 file changed, 13 insertions(+), 19 deletions(-) (limited to 'pyGHDL/dom/Concurrent.py') diff --git a/pyGHDL/dom/Concurrent.py b/pyGHDL/dom/Concurrent.py index 3b3c06f2e..71ee634cc 100644 --- a/pyGHDL/dom/Concurrent.py +++ b/pyGHDL/dom/Concurrent.py @@ -70,12 +70,6 @@ from pyVHDLModel.Concurrent import ( from pyGHDL.libghdl import Iir, utils from pyGHDL.libghdl.vhdl import nodes from pyGHDL.dom import DOMMixin, DOMException, Position -from pyGHDL.dom._Utils import ( - GetNameOfNode, - GetEntityInstantiationSymbol, - GetComponentInstantiationSymbol, - GetConfigurationInstantiationSymbol, -) from pyGHDL.dom.Range import Range from pyGHDL.dom.Symbol import ( ArchitectureSymbol, @@ -146,7 +140,7 @@ class EntityInstantiation(VHDLModel_EntityInstantiation, DOMMixin): @classmethod def parse(cls, instantiationNode: Iir, instantiatedUnit: Iir, label: str) -> "EntityInstantiation": - from pyGHDL.dom._Translate import GetGenericMapAspect, GetPortMapAspect + from pyGHDL.dom._Translate import GetName, GetGenericMapAspect, GetPortMapAspect entityId = nodes.Get_Entity_Name(instantiatedUnit) entitySymbol = GetEntityInstantiationSymbol(entityId) @@ -154,7 +148,7 @@ class EntityInstantiation(VHDLModel_EntityInstantiation, DOMMixin): architectureSymbol = None architectureId = nodes.Get_Architecture(instantiatedUnit) if architectureId != nodes.Null_Iir: - architectureSymbol = ArchitectureSymbol(GetNameOfNode(architectureId), entitySymbol) + architectureSymbol = ArchitectureSymbol(GetName(architectureId), entitySymbol) genericAssociations = GetGenericMapAspect(nodes.Get_Generic_Map_Aspect_Chain(instantiationNode)) portAssociations = GetPortMapAspect(nodes.Get_Port_Map_Aspect_Chain(instantiationNode)) @@ -230,13 +224,13 @@ class ProcessStatement(VHDLModel_ProcessStatement, DOMMixin): @classmethod def parse(cls, processNode: Iir, label: str, hasSensitivityList: bool) -> "ProcessStatement": - from pyGHDL.dom._Translate import GetDeclaredItemsFromChainedNodes, GetSequentialStatementsFromChainedNodes + from pyGHDL.dom._Translate import GetName, GetDeclaredItemsFromChainedNodes, GetSequentialStatementsFromChainedNodes sensitivityList = None if hasSensitivityList: sensitivityList = [] for item in utils.list_iter(nodes.Get_Sensitivity_List(processNode)): - sensitivityList.append(GetNameOfNode(item)) + sensitivityList.append(GetName(item)) declaredItems = GetDeclaredItemsFromChainedNodes(nodes.Get_Declaration_Chain(processNode), "process", label) statements = GetSequentialStatementsFromChainedNodes( @@ -490,7 +484,7 @@ class CaseGenerateStatement(VHDLModel_CaseGenerateStatement, DOMMixin): from pyGHDL.dom._Translate import ( GetExpressionFromNode, GetRangeFromNode, - GetNameFromNode, + GetName, ) expression = GetExpressionFromNode(nodes.Get_Expression(generateNode)) @@ -524,7 +518,7 @@ class CaseGenerateStatement(VHDLModel_CaseGenerateStatement, DOMMixin): nodes.Iir_Kind.Attribute_Name, nodes.Iir_Kind.Parenthesis_Name, ): - rng = GetNameFromNode(choiceRange) + rng = GetName(choiceRange) else: pos = Position.parse(alternative) raise DOMException( @@ -585,11 +579,11 @@ class ForGenerateStatement(VHDLModel_ForGenerateStatement, DOMMixin): GetDeclaredItemsFromChainedNodes, GetConcurrentStatementsFromChainedNodes, GetRangeFromNode, - GetNameFromNode, + GetName, ) spec = nodes.Get_Parameter_Specification(generateNode) - loopIndex = GetNameOfNode(spec) + loopIndex = GetName(spec) discreteRange = nodes.Get_Discrete_Range(spec) rangeKind = GetIirKindOfNode(discreteRange) @@ -599,7 +593,7 @@ class ForGenerateStatement(VHDLModel_ForGenerateStatement, DOMMixin): nodes.Iir_Kind.Attribute_Name, nodes.Iir_Kind.Parenthesis_Name, ): - rng = GetNameFromNode(discreteRange) + rng = GetName(discreteRange) else: pos = Position.parse(generateNode) raise DOMException( @@ -651,10 +645,10 @@ class ConcurrentSimpleSignalAssignment(VHDLModel_ConcurrentSimpleSignalAssignmen @classmethod def parse(cls, assignmentNode: Iir, label: str) -> "ConcurrentSimpleSignalAssignment": - from pyGHDL.dom._Translate import GetNameFromNode + from pyGHDL.dom._Translate import GetName target = nodes.Get_Target(assignmentNode) - targetName = GetNameFromNode(target) + targetName = GetName(target) waveform = [] for wave in utils.chain_iter(nodes.Get_Waveform_Chain(assignmentNode)): @@ -677,12 +671,12 @@ class ConcurrentProcedureCall(VHDLModel_ConcurrentProcedureCall, DOMMixin): @classmethod def parse(cls, concurrentCallNode: Iir, label: str) -> "ConcurrentProcedureCall": - from pyGHDL.dom._Translate import GetNameFromNode, GetParameterMapAspect + from pyGHDL.dom._Translate import GetName, GetParameterMapAspect callNode = nodes.Get_Procedure_Call(concurrentCallNode) prefix = nodes.Get_Prefix(callNode) - procedureName = GetNameFromNode(prefix) + procedureName = GetName(prefix) parameterAssociations = GetParameterMapAspect(nodes.Get_Parameter_Association_Chain(callNode)) return cls(concurrentCallNode, label, procedureName, parameterAssociations) -- cgit v1.2.3 From bee2616e7fed89c042f79592ddfafa2f6aea451e Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Fri, 14 Apr 2023 07:42:22 +0200 Subject: Fixes due to failing testcases. --- pyGHDL/dom/Concurrent.py | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'pyGHDL/dom/Concurrent.py') diff --git a/pyGHDL/dom/Concurrent.py b/pyGHDL/dom/Concurrent.py index 71ee634cc..4ffba28d1 100644 --- a/pyGHDL/dom/Concurrent.py +++ b/pyGHDL/dom/Concurrent.py @@ -115,9 +115,9 @@ class ComponentInstantiation(VHDLModel_ComponentInstantiation, DOMMixin): @classmethod def parse(cls, instantiationNode: Iir, instantiatedUnit: Iir, label: str) -> "ComponentInstantiation": - from pyGHDL.dom._Translate import GetGenericMapAspect, GetPortMapAspect + from pyGHDL.dom._Translate import GetName, GetGenericMapAspect, GetPortMapAspect - componentSymbol = GetComponentInstantiationSymbol(instantiatedUnit) + componentSymbol = ComponentInstantiationSymbol(instantiatedUnit, GetName(instantiatedUnit)) genericAssociations = GetGenericMapAspect(nodes.Get_Generic_Map_Aspect_Chain(instantiationNode)) portAssociations = GetPortMapAspect(nodes.Get_Port_Map_Aspect_Chain(instantiationNode)) @@ -142,8 +142,8 @@ class EntityInstantiation(VHDLModel_EntityInstantiation, DOMMixin): def parse(cls, instantiationNode: Iir, instantiatedUnit: Iir, label: str) -> "EntityInstantiation": from pyGHDL.dom._Translate import GetName, GetGenericMapAspect, GetPortMapAspect - entityId = nodes.Get_Entity_Name(instantiatedUnit) - entitySymbol = GetEntityInstantiationSymbol(entityId) + entityName = nodes.Get_Entity_Name(instantiatedUnit) + entitySymbol = EntityInstantiationSymbol(entityName, GetName(entityName)) architectureSymbol = None architectureId = nodes.Get_Architecture(instantiatedUnit) @@ -171,10 +171,10 @@ class ConfigurationInstantiation(VHDLModel_ConfigurationInstantiation, DOMMixin) @classmethod def parse(cls, instantiationNode: Iir, instantiatedUnit: Iir, label: str) -> "ConfigurationInstantiation": - from pyGHDL.dom._Translate import GetGenericMapAspect, GetPortMapAspect + from pyGHDL.dom._Translate import GetName, GetGenericMapAspect, GetPortMapAspect - configurationId = nodes.Get_Configuration_Name(instantiatedUnit) - configurationSymbol = GetConfigurationInstantiationSymbol(configurationId) + configurationName = nodes.Get_Configuration_Name(instantiatedUnit) + configurationSymbol = ConfigurationInstantiationSymbol(configurationName, GetName(configurationName)) genericAssociations = GetGenericMapAspect(nodes.Get_Generic_Map_Aspect_Chain(instantiationNode)) portAssociations = GetPortMapAspect(nodes.Get_Port_Map_Aspect_Chain(instantiationNode)) -- cgit v1.2.3 From d67bfa80c0c7d013a99636d7959cf433000ab2e7 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sat, 15 Apr 2023 10:43:09 +0200 Subject: Modifications due to changes in Symbols. --- pyGHDL/dom/Concurrent.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'pyGHDL/dom/Concurrent.py') diff --git a/pyGHDL/dom/Concurrent.py b/pyGHDL/dom/Concurrent.py index 4ffba28d1..303b6b96b 100644 --- a/pyGHDL/dom/Concurrent.py +++ b/pyGHDL/dom/Concurrent.py @@ -574,7 +574,7 @@ class ForGenerateStatement(VHDLModel_ForGenerateStatement, DOMMixin): @classmethod def parse(cls, generateNode: Iir, label: str) -> "ForGenerateStatement": - from pyGHDL.dom._Utils import GetIirKindOfNode + from pyGHDL.dom._Utils import GetIirKindOfNode, GetNameOfNode from pyGHDL.dom._Translate import ( GetDeclaredItemsFromChainedNodes, GetConcurrentStatementsFromChainedNodes, @@ -583,7 +583,7 @@ class ForGenerateStatement(VHDLModel_ForGenerateStatement, DOMMixin): ) spec = nodes.Get_Parameter_Specification(generateNode) - loopIndex = GetName(spec) + loopIndex = GetNameOfNode(spec) discreteRange = nodes.Get_Discrete_Range(spec) rangeKind = GetIirKindOfNode(discreteRange) -- cgit v1.2.3 From 636bdef4116fc635b2f4be04db7ab06543085121 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sat, 15 Apr 2023 19:10:33 +0200 Subject: Formatting by black. --- pyGHDL/dom/Concurrent.py | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'pyGHDL/dom/Concurrent.py') diff --git a/pyGHDL/dom/Concurrent.py b/pyGHDL/dom/Concurrent.py index 303b6b96b..ea46b4995 100644 --- a/pyGHDL/dom/Concurrent.py +++ b/pyGHDL/dom/Concurrent.py @@ -224,7 +224,11 @@ class ProcessStatement(VHDLModel_ProcessStatement, DOMMixin): @classmethod def parse(cls, processNode: Iir, label: str, hasSensitivityList: bool) -> "ProcessStatement": - from pyGHDL.dom._Translate import GetName, GetDeclaredItemsFromChainedNodes, GetSequentialStatementsFromChainedNodes + from pyGHDL.dom._Translate import ( + GetName, + GetDeclaredItemsFromChainedNodes, + GetSequentialStatementsFromChainedNodes, + ) sensitivityList = None if hasSensitivityList: -- cgit v1.2.3