From 9fca189af9677e435a42eaae1edd91e1098596ac Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Wed, 23 Jun 2021 10:06:39 +0200 Subject: Added handling of enumeration, array and record types. --- pyGHDL/dom/Literal.py | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) (limited to 'pyGHDL/dom/Literal.py') diff --git a/pyGHDL/dom/Literal.py b/pyGHDL/dom/Literal.py index 209712ba3..10d30b0fa 100644 --- a/pyGHDL/dom/Literal.py +++ b/pyGHDL/dom/Literal.py @@ -30,9 +30,11 @@ # # SPDX-License-Identifier: GPL-2.0-or-later # ============================================================================ +from pyGHDL.libghdl._types import Iir from pydecor import export from pyVHDLModel.VHDLModel import ( + EnumerationLiteral as VHDLModel_EnumerationLiteral, IntegerLiteral as VHDLModel_IntegerLiteral, FloatingPointLiteral as VHDLModel_FloatingPointLiteral, PhysicalIntegerLiteral as VHDLModel_PhysicalIntegerLiteral, @@ -47,10 +49,18 @@ from pyGHDL.dom._Utils import GetNameOfNode __all__ = [] +@export +class EnumerationLiteral(VHDLModel_EnumerationLiteral): + @classmethod + def parse(cls, literalNode: Iir) -> 'EnumerationLiteral': + literalName = GetNameOfNode(literalNode) + return cls(literalName) + + @export class IntegerLiteral(VHDLModel_IntegerLiteral): @classmethod - def parse(cls, node): + def parse(cls, node: Iir) -> 'IntegerLiteral': value = nodes.Get_Value(node) return cls(value) @@ -58,7 +68,7 @@ class IntegerLiteral(VHDLModel_IntegerLiteral): @export class FloatingPointLiteral(VHDLModel_FloatingPointLiteral): @classmethod - def parse(cls, node): + def parse(cls, node: Iir) -> 'FloatingPointLiteral': value = nodes.Get_Fp_Value(node) return cls(value) @@ -66,7 +76,7 @@ class FloatingPointLiteral(VHDLModel_FloatingPointLiteral): @export class PhysicalIntegerLiteral(VHDLModel_PhysicalIntegerLiteral): @classmethod - def parse(cls, node): + def parse(cls, node: Iir) -> 'PhysicalIntegerLiteral': value = nodes.Get_Value(node) unit = nodes.Get_Unit_Name(node) unitName = GetNameOfNode(unit) @@ -77,7 +87,7 @@ class PhysicalIntegerLiteral(VHDLModel_PhysicalIntegerLiteral): @export class PhysicalFloatingLiteral(VHDLModel_PhysicalFloatingLiteral): @classmethod - def parse(cls, node): + def parse(cls, node: Iir) -> 'PhysicalFloatingLiteral': value = nodes.Get_Fp_Value(node) unit = nodes.Get_Unit_Name(node) unitName = GetNameOfNode(unit) @@ -88,7 +98,7 @@ class PhysicalFloatingLiteral(VHDLModel_PhysicalFloatingLiteral): @export class CharacterLiteral(VHDLModel_CharacterLiteral): @classmethod - def parse(cls, node): + def parse(cls, node: Iir) -> 'CharacterLiteral': identifier = nodes.Get_Identifier(node) value = name_table.Get_Character(identifier) return cls(value) @@ -97,7 +107,7 @@ class CharacterLiteral(VHDLModel_CharacterLiteral): @export class StringLiteral(VHDLModel_StringLiteral): @classmethod - def parse(cls, node): + def parse(cls, node: Iir) -> 'StringLiteral': stringID = nodes.Get_String8_Id(node) value = name_table.Get_Name_Ptr(stringID) return cls(value) -- cgit v1.2.3 From d4e3bf7941e6826c0175f4768c31155bd5d98b0e Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Wed, 23 Jun 2021 10:23:23 +0200 Subject: Handle access types. --- pyGHDL/dom/Literal.py | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'pyGHDL/dom/Literal.py') diff --git a/pyGHDL/dom/Literal.py b/pyGHDL/dom/Literal.py index 10d30b0fa..a2e86b389 100644 --- a/pyGHDL/dom/Literal.py +++ b/pyGHDL/dom/Literal.py @@ -52,7 +52,7 @@ __all__ = [] @export class EnumerationLiteral(VHDLModel_EnumerationLiteral): @classmethod - def parse(cls, literalNode: Iir) -> 'EnumerationLiteral': + def parse(cls, literalNode: Iir) -> "EnumerationLiteral": literalName = GetNameOfNode(literalNode) return cls(literalName) @@ -60,7 +60,7 @@ class EnumerationLiteral(VHDLModel_EnumerationLiteral): @export class IntegerLiteral(VHDLModel_IntegerLiteral): @classmethod - def parse(cls, node: Iir) -> 'IntegerLiteral': + def parse(cls, node: Iir) -> "IntegerLiteral": value = nodes.Get_Value(node) return cls(value) @@ -68,7 +68,7 @@ class IntegerLiteral(VHDLModel_IntegerLiteral): @export class FloatingPointLiteral(VHDLModel_FloatingPointLiteral): @classmethod - def parse(cls, node: Iir) -> 'FloatingPointLiteral': + def parse(cls, node: Iir) -> "FloatingPointLiteral": value = nodes.Get_Fp_Value(node) return cls(value) @@ -76,7 +76,7 @@ class FloatingPointLiteral(VHDLModel_FloatingPointLiteral): @export class PhysicalIntegerLiteral(VHDLModel_PhysicalIntegerLiteral): @classmethod - def parse(cls, node: Iir) -> 'PhysicalIntegerLiteral': + def parse(cls, node: Iir) -> "PhysicalIntegerLiteral": value = nodes.Get_Value(node) unit = nodes.Get_Unit_Name(node) unitName = GetNameOfNode(unit) @@ -87,7 +87,7 @@ class PhysicalIntegerLiteral(VHDLModel_PhysicalIntegerLiteral): @export class PhysicalFloatingLiteral(VHDLModel_PhysicalFloatingLiteral): @classmethod - def parse(cls, node: Iir) -> 'PhysicalFloatingLiteral': + def parse(cls, node: Iir) -> "PhysicalFloatingLiteral": value = nodes.Get_Fp_Value(node) unit = nodes.Get_Unit_Name(node) unitName = GetNameOfNode(unit) @@ -98,7 +98,7 @@ class PhysicalFloatingLiteral(VHDLModel_PhysicalFloatingLiteral): @export class CharacterLiteral(VHDLModel_CharacterLiteral): @classmethod - def parse(cls, node: Iir) -> 'CharacterLiteral': + def parse(cls, node: Iir) -> "CharacterLiteral": identifier = nodes.Get_Identifier(node) value = name_table.Get_Character(identifier) return cls(value) @@ -107,7 +107,7 @@ class CharacterLiteral(VHDLModel_CharacterLiteral): @export class StringLiteral(VHDLModel_StringLiteral): @classmethod - def parse(cls, node: Iir) -> 'StringLiteral': + def parse(cls, node: Iir) -> "StringLiteral": stringID = nodes.Get_String8_Id(node) value = name_table.Get_Name_Ptr(stringID) return cls(value) -- cgit v1.2.3