From fb7ef864c019d325f3fc37125e6d6cdc50ae4b83 Mon Sep 17 00:00:00 2001
From: Patrick Lehmann <Paebbels@gmail.com>
Date: Thu, 12 Jan 2023 05:53:48 +0100
Subject: Dependency Graphs (#2308)

* Further fixes to the example code.

* Bumped dependencies.

* Fixed Debouncer example code.

* Some more cleanup.

* Black's opinion.

* Run with pyVHDLModel dev-branch.

* Fixed imports for Name.

* Fixed test case.

* Added a formatter to write dependency graphs and hierarchy as graphml.

* Improved GraphML formatting.

* Write compile order graph.

* Computing compile order.

* Bumped dependencies.

* Black's opinion.

* Fixed incorrect dependency.
---
 pyGHDL/dom/Sequential.py | 56 +++++++++++++++++++++---------------------------
 1 file changed, 24 insertions(+), 32 deletions(-)

(limited to 'pyGHDL/dom/Sequential.py')

diff --git a/pyGHDL/dom/Sequential.py b/pyGHDL/dom/Sequential.py
index 296f57f52..b698f1771 100644
--- a/pyGHDL/dom/Sequential.py
+++ b/pyGHDL/dom/Sequential.py
@@ -34,40 +34,32 @@ from typing import Iterable
 
 from pyTooling.Decorators import export
 
-from pyGHDL.dom.Concurrent import (
-    WaveformElement,
-    ParameterAssociationItem,
-)  # TODO: move out from concurrent?
-from pyGHDL.dom.Range import Range
-from pyVHDLModel.SyntaxModel import (
-    IfBranch as VHDLModel_IfBranch,
-    ElsifBranch as VHDLModel_ElsifBranch,
-    ElseBranch as VHDLModel_ElseBranch,
-    IfStatement as VHDLModel_IfStatement,
-    IndexedChoice as VHDLModel_IndexedChoice,
-    RangedChoice as VHDLModel_RangedChoice,
-    OthersCase as VHDLModel_OthersCase,
-    Case as VHDLModel_Case,
-    CaseStatement as VHDLModel_CaseStatement,
-    ForLoopStatement as VHDLModel_ForLoopStatement,
-    SequentialSimpleSignalAssignment as VHDLModel_SequentialSimpleSignalAssignment,
-    SequentialProcedureCall as VHDLModel_SequentialProcedureCall,
-    SequentialAssertStatement as VHDLModel_SequentialAssertStatement,
-    SequentialReportStatement as VHDLModel_SequentialReportStatement,
-    NullStatement as VHDLModel_NullStatement,
-    WaitStatement as VHDLModel_WaitStatement,
-    Name,
-    SequentialStatement,
-    ExpressionUnion,
-    SequentialChoice,
-    SequentialCase,
-)
-
+from pyVHDLModel.Base import ExpressionUnion
+from pyVHDLModel.Symbol import Symbol
+from pyVHDLModel.Sequential import SequentialStatement, SequentialChoice, SequentialCase
+from pyVHDLModel.Sequential import IfBranch as VHDLModel_IfBranch
+from pyVHDLModel.Sequential import ElsifBranch as VHDLModel_ElsifBranch
+from pyVHDLModel.Sequential import ElseBranch as VHDLModel_ElseBranch
+from pyVHDLModel.Sequential import IndexedChoice as VHDLModel_IndexedChoice
+from pyVHDLModel.Sequential import RangedChoice as VHDLModel_RangedChoice
+from pyVHDLModel.Sequential import Case as VHDLModel_Case
+from pyVHDLModel.Sequential import OthersCase as VHDLModel_OthersCase
+from pyVHDLModel.Sequential import IfStatement as VHDLModel_IfStatement
+from pyVHDLModel.Sequential import CaseStatement as VHDLModel_CaseStatement
+from pyVHDLModel.Sequential import ForLoopStatement as VHDLModel_ForLoopStatement
+from pyVHDLModel.Sequential import NullStatement as VHDLModel_NullStatement
+from pyVHDLModel.Sequential import WaitStatement as VHDLModel_WaitStatement
+from pyVHDLModel.Sequential import SequentialProcedureCall as VHDLModel_SequentialProcedureCall
+from pyVHDLModel.Sequential import SequentialSimpleSignalAssignment as VHDLModel_SequentialSimpleSignalAssignment
+from pyVHDLModel.Sequential import SequentialReportStatement as VHDLModel_SequentialReportStatement
+from pyVHDLModel.Sequential import SequentialAssertStatement as VHDLModel_SequentialAssertStatement
 
 from pyGHDL.libghdl import Iir, utils
 from pyGHDL.libghdl.vhdl import nodes
 from pyGHDL.dom import DOMMixin, Position, DOMException
 from pyGHDL.dom._Utils import GetNameOfNode
+from pyGHDL.dom.Range import Range
+from pyGHDL.dom.Concurrent import WaveformElement, ParameterAssociationItem  # TODO: move out from concurrent?
 
 
 @export
@@ -379,7 +371,7 @@ class SequentialSimpleSignalAssignment(VHDLModel_SequentialSimpleSignalAssignmen
     def __init__(
         self,
         assignmentNode: Iir,
-        target: Name,
+        target: Symbol,
         waveform: Iterable[WaveformElement],
         label: str = None,
     ):
@@ -405,7 +397,7 @@ class SequentialProcedureCall(VHDLModel_SequentialProcedureCall, DOMMixin):
     def __init__(
         self,
         callNode: Iir,
-        procedureName: Name,
+        procedureName: Symbol,
         parameterMappings: Iterable[ParameterAssociationItem],
         label: str = None,
     ):
@@ -490,7 +482,7 @@ class WaitStatement(VHDLModel_WaitStatement, DOMMixin):
     def __init__(
         self,
         waitNode: Iir,
-        sensitivityList: Iterable[Name] = None,
+        sensitivityList: Iterable[Symbol] = None,
         condition: ExpressionUnion = None,
         timeout: ExpressionUnion = None,
         label: str = None,
-- 
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