From db9c1fd3700995155b2d8a32d929b3d0dc9689e2 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Fri, 12 Jun 2020 07:47:46 +0200
Subject: vhdl: analyze and synth concurrent statements in vunit.  Fix #1366

---
 python/libghdl/thin/vhdl/nodes.py | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'python/libghdl/thin/vhdl')

diff --git a/python/libghdl/thin/vhdl/nodes.py b/python/libghdl/thin/vhdl/nodes.py
index 04aa11dcb..e25d2ef95 100644
--- a/python/libghdl/thin/vhdl/nodes.py
+++ b/python/libghdl/thin/vhdl/nodes.py
@@ -496,6 +496,11 @@ class Iir_Kinds:
         Iir_Kind.Psl_Rose,
         Iir_Kind.Psl_Fell]
 
+    Generate_Statement = [
+        Iir_Kind.If_Generate_Statement,
+        Iir_Kind.Case_Generate_Statement,
+        Iir_Kind.For_Generate_Statement]
+
     Composite_Subtype_Definition = [
         Iir_Kind.Array_Subtype_Definition,
         Iir_Kind.Record_Subtype_Definition]
-- 
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