From db9df06f901abe21976ae8f5d3b680965daef70b Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Tue, 22 Mar 2016 05:34:06 +0100
Subject: PSL: add clocked SERE, make endpoints visible from VHDL.

---
 src/grt/grt-rtis.ads | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src/grt/grt-rtis.ads')

diff --git a/src/grt/grt-rtis.ads b/src/grt/grt-rtis.ads
index 06e09647c..97687ba33 100644
--- a/src/grt/grt-rtis.ads
+++ b/src/grt/grt-rtis.ads
@@ -89,6 +89,8 @@ package Grt.Rtis is
       Ghdl_Rtik_Attribute_Stable,
       Ghdl_Rtik_Psl_Assert,
       Ghdl_Rtik_Psl_Cover,
+      Ghdl_Rtik_Psl_Endpoint,
+
       Ghdl_Rtik_Error);
    for Ghdl_Rtik'Size use 8;
 
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