From 418800b56e3296eec94e56707ebad7dcd1d1c6ee Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Wed, 18 Jan 2023 21:32:59 +0100 Subject: synth: create sub-instace for processes --- src/simul/simul-vhdl_elab.adb | 1 + 1 file changed, 1 insertion(+) (limited to 'src/simul/simul-vhdl_elab.adb') diff --git a/src/simul/simul-vhdl_elab.adb b/src/simul/simul-vhdl_elab.adb index eb481479b..8e2db63ad 100644 --- a/src/simul/simul-vhdl_elab.adb +++ b/src/simul/simul-vhdl_elab.adb @@ -1125,6 +1125,7 @@ package body Simul.Vhdl_Elab is if Get_Kind (Proc) in Iir_Kinds_Process_Statement then Proc_Inst := Make_Elab_Instance (Processes_Table.Table (I).Inst, Proc, Proc, Null_Node); + Set_Sub_Instance (Processes_Table.Table (I).Inst, Proc, Proc_Inst); Processes_Table.Table (I).Inst := Proc_Inst; Set_Instance_Const (Proc_Inst, True); Synth.Vhdl_Decls.Synth_Declarations -- cgit v1.2.3