From 768c62a76be455d299a065e5516fb8b7a917c019 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Thu, 12 Jan 2023 18:24:24 +0100
Subject: simul: handle PSL aborts

---
 src/simul/simul-vhdl_elab.adb | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

(limited to 'src/simul/simul-vhdl_elab.adb')

diff --git a/src/simul/simul-vhdl_elab.adb b/src/simul/simul-vhdl_elab.adb
index 03bd3f863..0ff4d2446 100644
--- a/src/simul/simul-vhdl_elab.adb
+++ b/src/simul/simul-vhdl_elab.adb
@@ -21,6 +21,11 @@ with Areapools;
 with Vhdl.Errors; use Vhdl.Errors;
 with Vhdl.Utils; use Vhdl.Utils;
 with Vhdl.Canon;
+with Vhdl.Canon_PSL;
+
+with PSL.Nodes;
+with PSL.Subsets;
+with PSL.Types;
 
 with Synth.Vhdl_Stmts;
 with Synth.Vhdl_Decls;
@@ -621,6 +626,23 @@ package body Simul.Vhdl_Elab is
             | Iir_Kind_Psl_Cover_Directive =>
             List := Get_PSL_Clock_Sensitivity (Proc);
             Gather_Sensitivity (Inst, Proc_Idx, List);
+            if Get_Kind (Proc) in Iir_Kinds_Psl_Property_Directive
+              and then Get_PSL_Abort_Flag (Proc)
+            then
+               declare
+                  use PSL.Types;
+                  use PSL.Nodes;
+                  Prop : constant PSL_Node := Get_Psl_Property (Proc);
+               begin
+                  if PSL.Subsets.Is_Async_Abort (Prop) then
+                     List := Create_Iir_List;
+                     Vhdl.Canon_PSL.Canon_Extract_Sensitivity
+                       (Get_Boolean (Prop), List);
+                     Gather_Sensitivity (Inst, Proc_Idx, List);
+                     Destroy_Iir_List (List);
+                  end if;
+               end;
+            end if;
             return;
          when Iir_Kind_Concurrent_Break_Statement =>
             List := Get_Sensitivity_List (Proc);
-- 
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