From 69ee33d1f0e4559b868068c955ef9c24f0438a11 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sat, 17 Sep 2022 16:36:34 +0200
Subject: synth: factorize code (reuse synth_constant_declaration)

---
 src/simul/simul-vhdl_elab.adb  | 2 +-
 src/simul/simul-vhdl_simul.adb | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/simul')

diff --git a/src/simul/simul-vhdl_elab.adb b/src/simul/simul-vhdl_elab.adb
index 9c89cfa81..68135502c 100644
--- a/src/simul/simul-vhdl_elab.adb
+++ b/src/simul/simul-vhdl_elab.adb
@@ -149,7 +149,7 @@ package body Simul.Vhdl_Elab is
 
       --  Set it to the default value.
       if Val.Val.Init /= null then
-         Copy_Memory (E.Val, Val.Val.Init.Mem, E.Typ.Sz);
+         Copy_Memory (E.Val, Get_Memory (Val.Val.Init), E.Typ.Sz);
       else
          Write_Value_Default (E.Val, E.Typ);
       end if;
diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb
index cbf51ff18..28c13d941 100644
--- a/src/simul/simul-vhdl_simul.adb
+++ b/src/simul/simul-vhdl_simul.adb
@@ -2759,6 +2759,7 @@ package body Simul.Vhdl_Simul is
                   Mark_Expr_Pool (Marker);
                   Val := Synth.Vhdl_Expr.Synth_Expression_With_Type
                     (C.Assoc_Inst, Get_Actual (C.Assoc), C.Formal.Typ);
+                  Val := Strip_Alias_Const (Val);
                   Signal_Associate_Cst
                     (Sig_Index (Signals_Table.Table (C.Formal.Base).Sig,
                                 C.Formal.Offs.Net_Off),
@@ -3190,7 +3191,6 @@ package body Simul.Vhdl_Simul is
       pragma Assert (Areapools.Is_Empty (Process_Pool));
 
       Synth.Flags.Severity_Level := Grt.Options.Severity_Level;
-      Synth.Flags.Flag_Simulation := True;
 
       if Flag_Interractive then
          Elab.Debugger.Debug_Elab (Vhdl_Elab.Top_Instance);
-- 
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