From abc76f1224bd8b42b8c5f49afc110c4ee1dda4af Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Wed, 11 Jan 2023 05:21:24 +0100 Subject: simul: handle psl assume directives --- src/simul/simul-vhdl_elab.adb | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/simul') diff --git a/src/simul/simul-vhdl_elab.adb b/src/simul/simul-vhdl_elab.adb index b2b0a4f2d..4948152cc 100644 --- a/src/simul/simul-vhdl_elab.adb +++ b/src/simul/simul-vhdl_elab.adb @@ -615,6 +615,7 @@ package body Simul.Vhdl_Elab is return; end if; when Iir_Kind_Psl_Assert_Directive + | Iir_Kind_Psl_Assume_Directive | Iir_Kind_Psl_Cover_Directive => List := Get_PSL_Clock_Sensitivity (Proc); Gather_Sensitivity (Inst, Proc_Idx, List); @@ -904,6 +905,7 @@ package body Simul.Vhdl_Elab is | Iir_Kind_Psl_Declaration => null; when Iir_Kind_Psl_Assert_Directive + | Iir_Kind_Psl_Assume_Directive | Iir_Kind_Psl_Cover_Directive | Iir_Kind_Concurrent_Break_Statement => Processes_Table.Append ((Proc => Stmt, -- cgit v1.2.3