From e7dba34e2b1f38f920cef3c4faed449921200668 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Wed, 11 Jan 2023 07:00:51 +0100 Subject: synth: improve support of PSL endpoints --- src/simul/simul-vhdl_elab.adb | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/simul') diff --git a/src/simul/simul-vhdl_elab.adb b/src/simul/simul-vhdl_elab.adb index 4948152cc..3e5acc3d8 100644 --- a/src/simul/simul-vhdl_elab.adb +++ b/src/simul/simul-vhdl_elab.adb @@ -902,7 +902,8 @@ package body Simul.Vhdl_Elab is pragma Assert (Is_Expr_Pool_Empty); Gather_Process_Sensitivity (Inst, Stmt, Processes_Table.Last); when Iir_Kind_Psl_Default_Clock - | Iir_Kind_Psl_Declaration => + | Iir_Kind_Psl_Declaration + | Iir_Kind_Psl_Endpoint_Declaration => null; when Iir_Kind_Psl_Assert_Directive | Iir_Kind_Psl_Assume_Directive -- cgit v1.2.3