From beadc8e7be3d5d58f6b76d405673642c58b23a30 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Wed, 30 Oct 2019 18:39:06 +0100 Subject: Add names for formal input gates/attributes. --- src/std_names.adb | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/std_names.adb') diff --git a/src/std_names.adb b/src/std_names.adb index d4722240c..aba33a9f6 100644 --- a/src/std_names.adb +++ b/src/std_names.adb @@ -654,6 +654,11 @@ package body Std_Names is Def ("ceil", Name_Ceil); Def ("log2", Name_Log2); + Def ("allconst", Name_Allconst); + Def ("allseq", Name_Allseq); + Def ("anyconst", Name_Anyconst); + Def ("anyseq", Name_Anyseq); + -- Verilog directives Def ("define", Name_Define); Def ("endif", Name_Endif); -- cgit v1.2.3