From f8f24837237c8705c21b4b46c9f8474b50786f95 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Thu, 19 May 2022 06:43:47 +0200 Subject: synth/elab-vhdl_values: use a proper type for signal_index --- src/synth/elab-vhdl_values-debug.adb | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/synth/elab-vhdl_values-debug.adb') diff --git a/src/synth/elab-vhdl_values-debug.adb b/src/synth/elab-vhdl_values-debug.adb index 193515e27..15da440e1 100644 --- a/src/synth/elab-vhdl_values-debug.adb +++ b/src/synth/elab-vhdl_values-debug.adb @@ -165,7 +165,8 @@ package body Elab.Vhdl_Values.Debug is case M.Typ.Kind is when Type_Bit | Type_Logic => - Put ("bit/logic"); + Put ("bit/logic: "); + Put_Uns32 (Uns32 (Read_U8 (M.Mem))); when Type_Vector => Put ("vector ("); Debug_Bound (M.Typ.Vbound, True); -- cgit v1.2.3