From 2a60624876cef4505bd05af8ac18276d37fffdf4 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sat, 2 May 2020 15:38:51 +0200
Subject: synth: preliminary support of sequential assertions.  For #1273

---
 src/synth/netlists-disp_vhdl.adb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/synth/netlists-disp_vhdl.adb')

diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb
index 6faf3337f..a4644d4f6 100644
--- a/src/synth/netlists-disp_vhdl.adb
+++ b/src/synth/netlists-disp_vhdl.adb
@@ -1248,7 +1248,7 @@ package body Netlists.Disp_Vhdl is
             Put_Line (";");
          when Id_Assert =>
             Disp_Template
-              ("  \l0: assert \i0 = '1' severity error;" & NL, Inst);
+              ("  \l0: postponed assert \i0 = '1' severity error;" & NL, Inst);
          when Id_Assume =>
             Disp_Template
               ("  \l0: assert \i0 = '1' severity warning; --  assume" & NL,
-- 
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