From 99dbf1376808a1bffb6886811d1585e34673b078 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Wed, 8 Feb 2023 11:31:04 +0100
Subject: synth: use same layout for records in memory as translate

---
 src/synth/synth-vhdl_eval.adb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/synth/synth-vhdl_eval.adb')

diff --git a/src/synth/synth-vhdl_eval.adb b/src/synth/synth-vhdl_eval.adb
index ec3b19e99..23bb3dac8 100644
--- a/src/synth/synth-vhdl_eval.adb
+++ b/src/synth/synth-vhdl_eval.adb
@@ -751,7 +751,7 @@ package body Synth.Vhdl_Eval is
    begin
       Bnd := (Dir => Dir_To, Left => 1, Right => Int32 (Len),
               Len => Uns32 (Len));
-      Typ := Create_Array_Type (Bnd, True, Styp.Uarr_El);
+      Typ := Create_Array_Type (Bnd, True, True, Styp.Uarr_El);
 
       Res := Create_Memory (Typ);
       for I in Str'Range loop
-- 
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