From c0b6dbfcc55da8cde4ad00782f0b27cd3abba6e6 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Mon, 6 Jun 2022 07:25:26 +0200 Subject: synth-vhdl_eval: recognize and handle to_stdulogicvector --- src/synth/synth-vhdl_eval.adb | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'src/synth/synth-vhdl_eval.adb') diff --git a/src/synth/synth-vhdl_eval.adb b/src/synth/synth-vhdl_eval.adb index 4574fa6f8..89743a5a8 100644 --- a/src/synth/synth-vhdl_eval.adb +++ b/src/synth/synth-vhdl_eval.adb @@ -2102,12 +2102,14 @@ package body Synth.Vhdl_Eval is when Iir_Predefined_Ieee_Numeric_Std_Touns_Nat_Nat_Uns | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Int - | Iir_Predefined_Ieee_Numeric_Std_Unsigned_To_Slv_Nat_Nat => + | Iir_Predefined_Ieee_Numeric_Std_Unsigned_To_Slv_Nat_Nat + | Iir_Predefined_Ieee_Numeric_Std_Unsigned_To_Suv_Nat_Nat => return Eval_To_Log_Vector (Uns64 (Read_Discrete (Param1)), Read_Discrete (Param2), Res_Typ); when Iir_Predefined_Ieee_Numeric_Std_Touns_Nat_Uns_Uns - | Iir_Predefined_Ieee_Numeric_Std_Unsigned_To_Slv_Nat_Slv => + | Iir_Predefined_Ieee_Numeric_Std_Unsigned_To_Slv_Nat_Slv + | Iir_Predefined_Ieee_Numeric_Std_Unsigned_To_Suv_Nat_Suv => return Eval_To_Log_Vector (Uns64 (Read_Discrete (Param1)), Int64 (Param2.Typ.Abound.Len), Res_Typ); -- cgit v1.2.3