From d340440584e3b60d11ec4ac88b34b3ed0dd25d5e Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Thu, 25 Aug 2022 04:12:17 +0200 Subject: synth: handle type left/right attributes --- src/synth/synth-vhdl_expr.adb | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'src/synth/synth-vhdl_expr.adb') diff --git a/src/synth/synth-vhdl_expr.adb b/src/synth/synth-vhdl_expr.adb index 62f41d3b5..6f33ff209 100644 --- a/src/synth/synth-vhdl_expr.adb +++ b/src/synth/synth-vhdl_expr.adb @@ -2078,6 +2078,20 @@ package body Synth.Vhdl_Expr is when Iir_Kind_Parenthesis_Expression => return Synth_Expression_With_Type (Syn_Inst, Get_Expression (Expr), Expr_Type); + when Iir_Kind_Left_Type_Attribute => + declare + T : Type_Acc; + begin + T := Synth_Type_Attribute (Syn_Inst, Expr); + return Create_Value_Discrete (T.Drange.Left, Expr_Type); + end; + when Iir_Kind_Right_Type_Attribute => + declare + T : Type_Acc; + begin + T := Synth_Type_Attribute (Syn_Inst, Expr); + return Create_Value_Discrete (T.Drange.Right, Expr_Type); + end; when Iir_Kind_Left_Array_Attribute => declare B : Bound_Type; -- cgit v1.2.3