From 946320e0984df406f0e3c50cd3db0fb49df5ec9b Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Sun, 22 May 2022 09:09:14 +0200 Subject: synth: merge value for type_vector and type_array --- src/synth/synth-vhdl_stmts.adb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/synth/synth-vhdl_stmts.adb') diff --git a/src/synth/synth-vhdl_stmts.adb b/src/synth/synth-vhdl_stmts.adb index 14302134d..02405dd25 100644 --- a/src/synth/synth-vhdl_stmts.adb +++ b/src/synth/synth-vhdl_stmts.adb @@ -858,8 +858,8 @@ package body Synth.Vhdl_Stmts is when Type_Discrete => return False; when Type_Vector => - if V.Typ.Vec_El = Logic_Type then - for I in 1 .. Size_Type (V.Typ.Vbound.Len) loop + if V.Typ.Arr_El = Logic_Type then + for I in 1 .. Size_Type (V.Typ.Abound.Len) loop if Ignore_Choice_Logic (Read_U8 (V.Val.Mem + (I - 1)), Loc) then return True; -- cgit v1.2.3