From f0900d17ff6ac00d3653e7aea5af166b603b155a Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Sun, 18 Sep 2022 08:57:27 +0200 Subject: synth-vhdl_stmts: minor renaming --- src/synth/synth-vhdl_stmts.adb | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'src/synth/synth-vhdl_stmts.adb') diff --git a/src/synth/synth-vhdl_stmts.adb b/src/synth/synth-vhdl_stmts.adb index b0726d03b..ffa780625 100644 --- a/src/synth/synth-vhdl_stmts.adb +++ b/src/synth/synth-vhdl_stmts.adb @@ -2137,16 +2137,16 @@ package body Synth.Vhdl_Stmts is end loop; end Synth_Subprogram_Associations; - procedure Synth_Subprogram_Association (Subprg_Inst : Synth_Instance_Acc; - Caller_Inst : Synth_Instance_Acc; - Inter_Chain : Node; - Assoc_Chain : Node) + procedure Synth_Subprogram_Associations (Subprg_Inst : Synth_Instance_Acc; + Caller_Inst : Synth_Instance_Acc; + Inter_Chain : Node; + Assoc_Chain : Node) is Init : Association_Iterator_Init; begin Init := Association_Iterator_Build (Inter_Chain, Assoc_Chain); Synth_Subprogram_Associations (Subprg_Inst, Caller_Inst, Init); - end Synth_Subprogram_Association; + end Synth_Subprogram_Associations; -- Create wires for out and inout interface variables. procedure Synth_Subprogram_Association_Wires -- cgit v1.2.3