From 688173587e76ee89b67b0c0aeb93385c0db08b22 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Thu, 4 Jul 2019 18:20:30 +0200 Subject: vhdl: rename Cover_Statement to Cover_Directive. --- src/vhdl/simulate/simul-simulation-main.adb | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/vhdl/simulate/simul-simulation-main.adb') diff --git a/src/vhdl/simulate/simul-simulation-main.adb b/src/vhdl/simulate/simul-simulation-main.adb index 461aeaad0..5af8acb55 100644 --- a/src/vhdl/simulate/simul-simulation-main.adb +++ b/src/vhdl/simulate/simul-simulation-main.adb @@ -436,7 +436,7 @@ package body Simul.Simulation.Main is if V then Nvec := (others => False); case Get_Kind (E.Stmt) is - when Iir_Kind_Psl_Cover_Statement + when Iir_Kind_Psl_Cover_Directive | Iir_Kind_Psl_Endpoint_Declaration => Nvec (0) := True; when others => @@ -483,7 +483,7 @@ package body Simul.Simulation.Main is (E.Instance, "psl assertion", E.Stmt, "assertion violation", 2); end if; - when Iir_Kind_Psl_Cover_Statement => + when Iir_Kind_Psl_Cover_Directive => if Nvec (S_Num) then if Get_Report_Expression (E.Stmt) /= Null_Iir then Execute_Failed_Assertion @@ -569,7 +569,7 @@ package body Simul.Simulation.Main is (To_Instance_Acc (E'Address), PSL_Assert_Finalizer'Access); end if; - when Iir_Kind_Psl_Cover_Statement => + when Iir_Kind_Psl_Cover_Directive => -- TODO null; when others => -- cgit v1.2.3