From 97d3a89195c8aeb981a7f4171b939c48ec4bdfaa Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Wed, 7 Aug 2019 05:59:50 +0200 Subject: vhdl: remove severity from cover, report and severity from assume. --- src/vhdl/simulate/simul-simulation-main.adb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/vhdl/simulate/simul-simulation-main.adb') diff --git a/src/vhdl/simulate/simul-simulation-main.adb b/src/vhdl/simulate/simul-simulation-main.adb index d6c6ba0ff..ae768b3d0 100644 --- a/src/vhdl/simulate/simul-simulation-main.adb +++ b/src/vhdl/simulate/simul-simulation-main.adb @@ -477,7 +477,7 @@ package body Simul.Simulation.Main is S_Num := Get_State_Label (S); pragma Assert (S_Num = Get_PSL_Nbr_States (E.Stmt) - 1); case Get_Kind (E.Stmt) is - when Iir_Kind_Psl_Assume_Directive => + when Iir_Kind_Psl_Assert_Directive => if Nvec (S_Num) then Execute_Failed_Assertion (E.Instance, "psl assertion", E.Stmt, -- cgit v1.2.3